MPC855TCVR50D4 Freescale Semiconductor, MPC855TCVR50D4 Datasheet - Page 83

• Manufacturer Part Number: MPC855TCVR50D4
• Description: IC MPU POWERQUICC 50MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC855TCVR50D4

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: -40C to 95C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.8.1 Termination of Unused Signals
If the JTAG interface and COP header are not used, Freescale recommends the following connections:
Freescale Semiconductor
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TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in
case a JTAG interface may need to be wired onto the system in future debug situations.
Tie TCK to OV
incorrect data into the device.
No connection is required for TDI, TMS, or TDO.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Figure
DD
through a 10 kΩ resistor. This prevents TCK from changing state and reading
53. If this is not possible, the isolation resistor allows future access to TRST in
System Design Information
83