MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 156

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
The assertion of CIIN during the second, third, or fourth cycle of a burst
the execution unit uses that data.
transferred into the appropriate cache. However, the burst operation aborts
The assertion of CIIN during the first cycle of a burst operation causes the
data to be latched by the processor, and if the requested operand is aligned
corresponding cache. In addition, the MC68030 negates CBREQ, and the burst
operation is aborted. If a portion of the requested operand remains to be
address with CBREQ negated.
operation prevents the data during that cycle from being loaded into the
appropriate cache and causes CBREQ to negate, aborting the burst operation.
The premature negation of the CBACK signal during the burst operation
causes the current cycle to complete normally, loading the data successfully
and CBREQ negates.
A bus error occurring during a burst operation also causes the burst operation
to abort. If the bus error occurs during the first cycle of a burst (i.e., before
associated cache line is marked "invalid". If the access is a data cycle, ex-
ception processing proceeds immediately. If the cycle is for an instruction
fetch, a bus error exception is made pending. This bus error is processed
to that cycle is marked invalid, but the processor does not take an exception
struction cache burst, the data from the aborted cycle is completely ignored.
the processor. If the second cycle is for a portion of a misaligned data operand
fetch and a bus error occurs, the processor terminates the burst operation
for the second cycle of the burst, the data cache results in a miss, and a
then takes an exception.
(the entire operand is latched in the first cycle), the data is passed on to the
instruction pipe or execution unit. However, the data is not loaded into its
read (due to misalignment), a second read cycle is initiated atthe appropriate
However, if the data for the cycle contains part of the requested operand,
burst mode is entered), the data read from the bus is ignored, and the entire
only if the execution unit attempts to use either instruction word. Refer to
11.2.2 Instruction Pipe for more information about pipeline operation.
For either cache, when a bus error occurs after the burst mode has been
entered (that is, on the second cycle or later), the cache entry corresponding
(the microsequencer has not yet requested the data). In the case of an in-
Pending instruction prefetches are still pending and are subsequently run by
and negates CBREQ. Once the burst terminates, the microsequencer requests
a read cycle for the second portion. Since the burst terminated abnormally
second external cycle is required. If BERR is again asserted, the MC68030
MC68030 USER'S MANUAL
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