MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 591

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

I
Operation Word CIR, 10-31
Operations, Bit Field, 3-31
Ordering Information, 14-1
Not Ready Format Word, 10-23
Notation, Instruction Description, 3-3
Null Primitive, 10-37, 10-38
Number of Table Levels, 9-68
OCS Signal, 5-5, 7-4, 7-31ff
Operand, Misaligned, 7-13, 7-19
Operand Address CIR, 10-33
Operand CIR, 10-33
Operand Cycle Start Signal, 5-5, 7-4, 7-27ff
Operands, 2-1
Operation,
Organization,
Overlap, 11-7
Performance Tradeoffs, 11-1
Pipeline, 1-12, 11-2
Nested Subroutine Calls, 3-30
No Operation Instruction, 7495
Non-DMA Coprocessor, 10-5
NOP Instruction, 7-95
Normal Processing State, 4-1
Package Dimensions, 14-2
Paging,
Pin Assignment, 14-2, 14-3
Pin Assignments,
MOVES Instruction, 7-74
Multiple Exceptions, 8-23
Multiplexer, Data Bus, Internal to External, 7-11
Multiprocessor Instructions, 3-13
M68000 Family, 1-4, 2-36
INDEX-8
Concurrent, 10-3
Reset, 7-103
Retry, 7-89
Cache, 6-3
Table, 9-37, 9-38
GND, 12-46
VCC, 12-46
Burst, 7-59
Halt, 7-91
Data Port, 7-8
Memory Data, 2-5
Register Data, 2-2
Implementation Example System, 9-72
Summary, A-l-A-3
- - O - -
MC68030 USER'S MANUAL
Pipeline Refill Signal, 5-10, 6-5
Pipeline Synchronization, 3-32
Pipelined Burst Mode Static RAM, 12-18-12-24
Pointer,
Post-Instruction Stack Frame, 10-60
Power Supply Connections, 5-11
Pre-lnstruction Stack Frame, 10-57
Primitive,
Primitive Processing Exception, 10-66
Priority, Exception, 8-16
Privilege Level,
Privilege Violation Exception, 8-11, 10-69
Privileged Instructions, 8-11
Processing, Exception, 4-6
Processor Activity,
Processor Generated Reset Timing, 7-106
Processor Resource Block Diagram, 11-3
Program Control Instructions, 3-11
Program Counter
Programming Model, 1-4, 9-4
Protection, 9-43
CPU Root, 1-9, 2-5, 9-23, 9-52, 9-54, 9-65
Supervisor Root, 1-9, 2-5~ 9-23, 9-52, 9-54; 9-65
Coprocessor Response, 10-11, 10-36
Evaluate and Transfer Effective Address, 10-42
Evaluate Effective Address and Transfer Data,
Null, 10-37, 10-38
Supervisor Check, 10-40
Take Address and Transfer Data, 10-48
Take Mid-Instruction Exception, 10-58
Take Post-Instruction Exception, 10-60
Take Pre-lnstruction Exception, 10-56
Transfer from Instruction Stream, 10-41
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Write to
Changing, 4-4
Supervisor, 4-3
User, 4-3
Even Alignment, 11-9
Odd Alignment, 11-10
Indirect index (8-Bit Displacement) Mode, 2-12
Supervisor Only, 9-48
Write, 9-48
Busy, 10-36
Indirect Displacement Mode, 2-12
Indirect Index (Base Displacement) Mode, 2-13
Memory Indirect Postindexed Mode, 2-14
Memory Indirect Preindexed Mode, 2-14
MMU, 9-4
10-43
10-52
10-46
Previously Evaluated Effective Address,
Main Processor Control Register, 10-50
Multiple Coprocessor Registers, 10-52
Multiple Main Processor Registers,
Operation Word, 10-40
Single Main Processor Register, 10-50
Status Register and ScanPC, 10-55
to/from Top of Stack, 10-49
MOTOROLA