MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 291

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8
8.1.13 Return from Exception
8-24
The priority scheme is very important in determining the order in which
As a general rule, the lower the priority of an exception, the sooner the
trap, trace, and interrupt exceptions are pending, the exception processing
for the trap occurs first, followed i m m e d i a t e l y by exception processing for
the trace and then for the interrupt. When the processor resumes normal
exception handlers execute when several exceptions occur at the same time.
handler routine for that exception executes. For example, if simultaneous
to the reset exception; its handler is executed first even though it has the
After the processor has completed exception processing for all pending ex-
instruction execution, it is in the interrupt handler, which returns to the trace
handler, which returns to the trap exception handler. This rule does not apply
highest priority because the reset operation clears all other exceptions.
ceptions, the processor resumes normal instruction execution at the address
in the vector for the last exception processed. Once the exception handler
prior to the exception (if possible). The RTE instruction returns from the
has completed execution, the processor must return to the system context
handler to the previous system context for any exception.
0.0 is the highest priority, 4.2 is the lowest.
Priority
Group/
0
2
3
4
1
O.0- Reset
2.0-- BKPT #n, CHK, CHK2, cp Mid-/nstruc- Exception processing is part of instruction
4.0 -- cp Post-Instruction
3.0 -- Illegal Instruction, Line A, Unimple- Exception processing begins before in-
4.1 -- Trace
4.2 -- Interrupt
1.1 -- Bus Error
1.0--Address Error
tion, cp Protocol Violation, cp- execution.
TRAPcc, Divide by Zero, RTE, TRAP
#n, TRAPV, MMU Configuration
merited Line F, Privilege Violation, struction is executed.
cp Pre-lnstruction
Table 8-5. Exception Priority Groups
Relative Priority
Exception and
MC68030 USER'S MANUAL
Aborts all processing (instruction or ex-
ception) and does not save old context.
ception) and saves internal context.
Suspends processing (instruction or ex-
Exception processing begins when current
instruction or previous exception process-
ing is completed.
Characteristics
MOTOROLA