MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 403

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

O
10.2.2.2.2 Protocol.
10-16
• coprocessor can return a response primitive to request services necessary
the instruction can include extension words to provide this information. The
word following the F-line operation word to the condition CIR. The main
to evaluate the condition. The operation of the cpScc instruction depends on
the condition evaluation indicator returned to the main processor by the
the main processor sets the byte at the effective address to TRUE (all bits
The first word of the cpScc instruction is the F-line operation word. This word
The second word of the cpScc instruction format contains the coprocessor
condition selector in bits [0-5]. Bits [6-15] of this word are reserved by
struction.
coprocessor condition selector field, is determined by the coprocessor de-
sign.
The final portion of the cpScc instruction format contains zero to five effective
address extension words. These words contain any additional information
coprocessor. When the coprocessor returns the false condition indicator, the
contains the CplD field in bits [9-11] and 001 in bits [8:6] to identify the cpScc
instruction. The lower six bits of the F-line operation word are used to encode
an M68000 Family effective addressing mode (refer to 2.5 EFFECTIVE
DRESS ENCODING S U M M A R Y ) .
Motorola and should be zero to ensure compatibility with future M68000
products. This word is written to the condition CIR to initiate the cpScc in-
If the coprocessor requires additional information to evaluate the condition,
number of these extension words, which follow the word containing the
required to calculate the effective address specified by bits [0-5] of the
F-line operation word.
MC68030 transfers the condition selector to the coprocessor by writing the
processor then reads the response CIR to determine its next action. The
main processor evaluates the effective address specified by bits [0-5] of the
F-line operation word and sets the byte at that effective address to FALSE
(all bits cleared). When the coprocessor returns the true condition indicator,
set to one).
Figure i0-8 shows the protocol for the cpScc instruction. The
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