MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 535

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12
12-10
following logic works correctly with the MC68030's on-chip internal-to-
The need for byte select signals is best illustrated by an example. Consider
transfer requires three bus cycles to complete. The first bus cycle transfers
the most significant byte of the long word on D16-D23. The second bus cycle
transfers a word on D16-D31, and the last bus cycle transfers the least sig-
those bytes which are not used these transfers, a unique byte data strobe
widths.
of the data bus for any given bus transfer are a function of the size (SIZ0/
dividual strobes or select signals can be generated by decoding these four
signals for every bus cycle. Devices residing on 8-bit ports can utilize data
strobe (DS) alone since there is only one valid byte for any transfer.
over its full bus width (as indicated by DSACKx or STERM). While instructions
with any alignment and size. Because the MC68030 assumes that the entire
satisfy this requirement, the R/W signal must be included in the byte select
chronous 32-bit port and unmapped byte select signals for other memory
The MC68030 assumes that 16-bit ports are situated on data lines D16-D31,
and that 8-bit ports are situated on data lines D24-D31. This ensures that the
external data bus multiplexer. Refer to SECTION 7 BUS OPERATION for more
details on the dynamic bus sizing mechanism.
a long-word write cycle to an odd address in word-organized memory. The
nificant byte of the original long word on D24-D31. In order not to overwrite
must be generated for each byte when using devices with 16- and 32-bit port
For noncachable read cycles and all write cycles, the required active bytes
SlZl) and lower address (A0/A1) outputs and are shown in Table 12-1. In-
During cachable read cycles, the addressed device must provide valid data
are always prefetched as long-word-aligned accesses, data fetches can occur
data bus port size contains valid data, cachable data read bus cycles must
provide as much data as signaled by the port size during a bus cycle. To
logic for the MC68030.
Figure 12-6 shows a block diagram of an MC68030 system with two memory
banks. The PAL provides memory-mapped byte select signals for an asyn-
banks or ports. Figure 12-7 provides sample equations for the PAL.
• DSACK1, DSACK0 = Data transfer and size acknowledge. Driven by an
• STERM = Synchronous termination. Driven by a 32-bit synchronous
port only.
MC68030 USER'S MANUAL
asynchronous port to indicate the actual bus width
of the port.
MOTOROLA