MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 595

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

I
Timing Table,
Trace Exception, 8-12, 10-70
Tradeoffs, Performance,11-1
Transfer,
Transfer Main Processor Control Register Primitive,
Transfer Multiple Coprocessor Registers Primitive,
Timing (Continued)
Transfer Multiple Main Processor Registers
Transfer Operation Word Primitive, 10-40
Transfer Single Main Processor Register Primitive,
Transfer Size Signals, 5-4, 7-4, 7-8, 7-9-7-14, 7-22ff
Transfer Status Register and ScanPC Primitive,
INDEX-12
Write, Long-Word, 7-12
Arithmetic/Logical Instruction, 11-40
Jump Effective Address, 11-35
Table Search, 11-51
Word to Byte, 7-13
Table Search, 11-39
Write, Word, 7-14
Binary Coded Decimal Instruction, 11-43
Bit Field Instruction, 11-47
Bit Manipulation Instruction, 11-46
Calculate Effective Address, 11-30
Calculate Immediate Effective Address, 11-32
Conditional Branch Instruction, 11-48
Control Instruction, 11-49
Exception Related
Extended Instruction, 11-43
Fetch Effective Address, 11-26
Fetch Immediate Effective Address, 11-28
MMU
MOVE Instruction, 11-37
Restore Operation, 11-51
Save Operation, 11-51
Shift/Rotate Instruction, 11-45
Single Operand Instruction, 11-44
Signals, 12-38
Long Word to Long Word, Misaligned Cachable,
Long Word to Word, 7-11
Misaligned
10-50
10-52
Primitive, 10-52
10-50
10-55
7-20
Word to Word, 7-17
Word to Word, Timing, 7-18
Write Cycle, Wait States, CLOUT Asserted, 7-53
immediate, 11-42
Instruction, 11-50
Operation, 11-50
Effective Address, 11-58
Instruction, 11-60
Special Purpose, 11-39
Cachable Word to Long Word, 7-17
Cachable Word to Word, 7-20
Long Word to Long Word, 7-20
Long Word to Word, 7-17
MC68030 USER'S MANUAL
Transparent Translation Registers, 1-9, 2-5, 9-16,
Transfer to/from Top of Stack Primitive, 10-49
Translation, Address, 9-13
Translation Control Register, 1-9, 2-5, "9-8, 9-54
Translation Table Descriptors, 9-10, 9-20
Translation Table Tree, 9-5, 9-7, 9-8, 9-12, 9-30,
Translation Tree, Supervisor, 9-48
Tree, Translation Table, 9-5, 9-7, 9-8, 9-12, 9-30,
TT0, 1-9, 2-5, 9-16, 9-57
TT1, 1-9, 2-5, 9q6, 9-57
Two Clock Synchronous Static RAM, 12-18-12-20
Types,
Unimplemented Instruction Exception, 8-9
Unit,
Units, Floating Point, 12-5
Unused Descriptor Bits, 9-71
User Privilege Level, 4-2, 4-4
User Program Stack, 2-38
Valid Format Word, 10-24
Vallocate Routine, 9-78
VBR, 1-8, 2-5
VCC Pin Assignments, 12-46
Vector
Vectors, Exception, 4-6
Virtual Machine, 1-12
Virtual Memory, 1-12, 9-77
WA Bit, 6-21
Wait States, 11-18
Window,
Word, Special Status, 8-28
Word Read Cycle, Asynchronous, 32-Bit Port,
Word to Byte Transfer, 7-13
Word to Long-Word Transfer, Misaligned, 7-17
Word to Word Transfer, Misaligned Cachable, 7-20
9-47, 9-48, 9-65
9-55
9-47, 9-48, 9-65
Address Space, 4-3
Protection Example, 9-50
Data, 1-10
Execution, 6-16
Memory Management, 1-15, 7-3, 7-36, 7-43, 9-1,
Base Register, 1-8, 2-5
Numbers, Exception, 8-1
Asynchronous Sample, 7-3
Timing, 7-33
11-5, 12-4
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V
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