MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 429

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

IO
1 0 . 4 . 8
10-42
violation exception processing. Figure 10-28 shows the format of the evaluate
This primitive uses the CA and PC bits as previously described.
the effective address is calculated, the resulting 32-bit value is written to the
transferred. When execution of the primitive has completed, the scanPC has
word following the last word transferred. The main processor transfers the
to the operand CIR. If the length field is not an even multiple of four bytes,
the fast two bytes from the instruction stream are transferred using a word
write to the operand CIR.
The evaluate and transfer effective address primitive evaluates the effective
address specified in the coprocessor instruction operation word and transfers
the result to the coprocessor. This primitive applies to general category in-
structions. If this primitive is issued by the coprocessor during the execution
of a conditional category instruction, the main processor initiates protocol
and transfer effective address primitive.
When the main processor reads this primitive while executing a general
category instruction, it evaluates the effective address specified in the in-
struction. At this point, the scanPC contains the address of the first of any
the scanPC by two after it references each of these extension words. After
operand address CIR.
The MC68030 only calculates effective addresses for control alterable ad-
the instruction by writing a $0001 to the control CIR and initiates F-line em-
TIONS).
location pointed to by the scanPC when the primitive is read by the main
processor, and the scanPC is incremented after each word or long word is
operands from the instruction stream using a sequence of long-word writes
required effective address extension words. The main processor increments
dressing modes in response to this primitive. If the addressing mode in the
operation word is not a control alterable mode, the main processor aborts
ulation exception processing (refer to 10.5.2.2 F-LINE
been incremented by the total number of bytes transferred and points to the
CA
15
Figure 10-28. Evaluate and Transfer Effective Address Primitive Format
E v a l u a t e
PC
14
13
0
a n d T r a n s f e r
12
0
11
1
MC68030 USER'S MANUAL
10
0
E f f e c t i v e
9
1
8
0
A d d r e s s
0
7
0
6
0
P r i m i t i v e
5
E M U L A T O R EXCEP-
0
4
0
3
0
MOTOROLA
2
0
1
0
0