MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 228

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
State 3
State 4
State 5
State 6
the synchronous input setup and hold times for all rising edges of the clock
while AS is asserted. If STERM is negated at the beginning of $2, wait
states are inserted after $2, and STERM is sampled on every rising edge
The processor maintains AS, DS, and DBEN asserted during $3. It also
The external device must keep the data driven throughout the synchronous
within one clock after asserting STERM; otherwise, the processor may
At the beginning of $4, the processor tests the level of STERM. This state
to burst fill cycles. If STERM is recognized, the processor latches the in-
word of the burst. If STERM is negated at the beginning of $4, wait states
the states of CBACK and CIIN are latched at the time STERM is recognized.
The assertion of CBACK at this time indicates that the burst operation
Since CIIN, CBACK, and STERM are synchronous signals, they must meet
of the clock thereafter until it is recognized. Once STERM is recognized,
data is latched on the next falling edge of the clock (corresponding to the
beginning of $3).
holds the address valid during $3 for continuation of the burst.
SIZ0-SIZ1, and FC0-FC2 also remain valid throughout $3.
signifies the beginning of burst mode, and the remaining states correspond
coming
are inserted instead of S4 and $5, and STERM is sampled on every rising
edge of the clock thereafter until it is recognized. As for synchronous cycles,
should continue, and the assertion of CIIN indicates that the data latched
at the end of $4 should not be cached and that the burst should abort.
The processor maintains all the signals on the bus driven throughout S5
for continuation of the burst. The same hold times for STERM and data
described for S3 apply here.
This state is identical to S4 except that once STERM is recognized, the third
hold time for data from the beginning of $3. The device must negate STERM
inadvertently use STERM prematurely for the next burst access. STERM
need not be negated if subsequent accesses do not require wait cycles.
long word of data for the burst is latched at the end of $6.
data at the end of $4. This data corresponds to the second long
MC68030 USER'S MANUAL
R/W,
7-67
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