MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 255

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7
7-94
7.5.4 Double Bus Fault
the data bus is placed in the high-impedance state, and bus control signals
size, and read/write signals are again driven to their previous states. The
assert the ]PEND signal as appropriate.
When a bus error or an address error occurs during the exception processing
sequence for a previous bus error, a previous address error, or a reset ex-
ception, the bus or address error causes a double bus fault. For example,
the processor attempts to stack several words containing information about
the state of the machine while processing a bus error exception. If a bus
considered a double bus fault. Only an external reset operation can restart
ARBITRATION).
The MC68030 indicates that a double bus fault condition has occurred by
continuously asserting the STATUS signal until the processor is reset. The
A second bus error or address error that occurs after exception processing
does not cause a double bus fault. A bus cycle that is retried does not con-
stitute a bus error or contribute to a double bus fault. The processor continues
to retry the same bus cycle as long as the external hardware requests it.
to trace single bus cycles, single instructions, or changes in program flow.
These processor capabilities, along with a software debugging package, give
complete debugging flexibility.
When the processor completes a bus cycle with the HALT signal asserted,
size, and read/write signals remain in the same statel The halt operation has
arbitration occurs while the MC68030 is halted, the address and control sig-
nals are also placed in the high-impedance state. Once bus mastership is
processor does not service interrupt requests while it is halted, but it may
error exception occurs during the stacking operation, the second error is
a halted processor. However, bus arbitration can still occur (refer to 7.7 BUS
processor asserts STATUS for one, two, or three clock periods to signal other
microsequencer status indications. Refer to SECTION 12 APPLICATIONS IN-
FORMATION for a description of the interpretation of the STATUS signal.
has completed (during the execution of the exception handler routine or later)
step operation and the software trace capability allow the system debugger
are driven inactive (not high-impedance state); the address, function code,
no effect on bus arbitration (refer to 7.7 BUS ARBITRATION). When bus
returned to the MC68030, if HALT is still asserted, the address, function code,
MC68030 USER'S MANUAL
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