MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 112

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8.2 CPM Loading
This section primarily deals with the CPM loading of the MH360 and 860MH. As the CPM
architecture is identical on both devices, the performance for a given clock frequency is
identical. Compared to standard protocols, the QMC protocol places more demands on the
CPM RISC because it requires the CPM to handle all of the bit manipulation normally
implemented with hardware support built into the SCCs.
The SCC operates transparently in QMC mode. The SCC’s main function is serial-to-
parallel conversion of the data stream out of the time slot assigner, and parallel-to-serial
conversion of the data stream gated into the time slot assigner. All bit manipulating is done
in the CPM RISC software or hardware. Thus, the CPM has a much higher load when
operating in QMC mode, even if all time slots are concatenated to one logical channel. This
loading is reflected in the measured performance.
Table 8-2 gives loading guidelines. The table assumes a single SCC running at 100% of the
CPM bandwidth. For each protocol supported, the table gives the ratio of the SCC bit rate
versus clock frequency, and the maximum serial throughput at standard frequencies.
SCC1: 10-Mbps Ethernet; SCC2: 16 x 64-Kbps QMC;
SCC3: 16 x 64-Kbps QMC; SCC4: 64-Kbps HDLC.
TDM bit rate = 2.048 Mbps
SCC1: 10-Mbps Ethernet; SCC2: 12 x 64-Kbps QMC;
SCC3: 12 x 64-Kbps QMC; SCC4: 64-Kbps HDLC.
TDM bit rate = 1.544 Mbps
SCC1: 24-channel QMC; SCC2: 24-channel QMC.
Serial bit rate 2 x 1.544 Mbps — 2 x T1
SCC1: 10-Mbps Ethernet SCC2: 24-channel QMC;
SCC3: 24 Channel QMC.
Serial bit rate 2 x 1.544 Mbps — 2 x T1
SCC1: 32-channel QMC; SCC2: 32-channel QMC.
Serial bit rate 2 x 2.048 Mbps (E1/CEPT)
Transparent
HDLC
UART
Protocol
Table 8-1. Common QMC Configurations (Continued)
Protocols Selected
Freescale Semiconductor, Inc.
For More Information On This Product,
1 : 3.125 FD
1 : 3.125 FD
1 : 10.4 FD
SCC Rate: Clock Frequency
Table 8-2. CPM Performance Table
Mbps: MHz
Go to: www.freescale.com
QMC Supplement
8
8
2.4
25 MHz
25 MHz
Mbps
No
No
No
No
No
Maximum Serial Throughput
10.56
10.56
3.168
Frequency Supported
33 MHz
33 MHz
Mbps
Yes
Yes
No
No
No
12.8
12.8
3.84
40 MHz
40 MHz
Mbps
Yes
Yes
Yes
No
No
16
16
4.8
50 MHz
Mbps
50 MHz
Yes
Yes
Yes
Yes
Yes