MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 121

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Table 9-1. Time Slot Assignment Table Entry Fields for Receive (MSC) (Continued)
Table 9-2 describes the fields in the time slot assignment table for transmit (TSATTx) for
MSC operation.
L
Rx channel
pointer
Mask(0–7)
V
W
L
Tx channel
pointer
Mask(0–7)
Name
Field
Table 9-2. Time Slot Assignment Table Entry Fields for Transmit (MSC)
Valid bit—The valid bit indicates whether this time slot is valid.
0 Logic 1 is transmitted. If the Tx signal of the TDM interface is programmed to be an open drain
1 Data is transmitted from its associated buffer in combination with the mask bit settings.
Wrap bit—The wrap bit identifies the last entry in TSATTx.
0 This is not the last time slot in the frame.
1 The RISC processor wraps around and handles time slot 0 or the first 8 bits of data in the SCC in
Last bit—Identifies the last subchannel in a time slot.
0 This is not the last subchannel in the time slot.
1 This is the last sub channel within an 8-bit time slot.The RISC processor handles the next time
This field of the TSATTx entry identifies a data channel which is routed to this time slot. The actual
channel pointer is 11 bits long, and contains the starting address of the channel-specific parameter
area (address of TBASE). The 5 most significant bits are taken from TSATTx channel pointer field,
and the 6 least significant bits are always internally set to zero. For MSC protocol, the addressing
range is 2 Kbytes.
Mask bits—Identifies the valid bits in this time slot for subchanneling support. For 8-bit resolution, all
mask bits should be set to 1. For a valid channel with an unmasked bit (1), the bit position is filled
according to the protocol. A valid channel with a masked bit (0) transmits a logic high (1).
Last bit—Identifies the last subchannel in a time slot.
0 This is not the last subchannel in the time slot.
1 This is the last sub channel within an 8-bit time slot.The RISC processor handles the next time
This field of the TSATRx entry identifies the data channel that is routed to this time slot. The actual
channel pointer is 11 bits long, and contains the starting address of the channel-specific parameter
area (address of TBASE). The 5 most-significant bits are taken from TSATRx, and the 6 least-
significant bits are always internally set to zero. For the MSC operation, the addressing range is
2 Kbytes.
Mask bits—These 8 bits identify the valid bits in this time slot for subchanneling support. For 8-bit
resolution, all mask bits should be set to 1. Any unmasked bit (1) is processed in the receiver for a
valid time slot. Any masked bit (0) is ignored by the receiver for a valid channel and no bit counter is
affected.
output (port B programming), other devices can transmit on nonvalid time slots.
the next request. The next request is identified by a frame synchronization pulse.
slot transferred to the TSA in the next request.
slot transferred from the TSA in the next request.
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 9. Multi-Subchannel (MSC) Microcode
Go to: www.freescale.com
Description
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