MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 6

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Paragraph
Number
2.1.9
2.2
2.3
2.4
2.4.1
2.4.1.1
2.4.1.2
2.4.1.3
2.4.1.4
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.2.4
2.4.2.5
3.1
3.2
4.1
4.1.1
4.1.2
4.1.3
4.2
4.3
4.4
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
Global Multichannel Parameters ..........................................................................2-5
Multiple SCC Assignment Tables ......................................................................2-10
Channel-Specific Parameters..............................................................................2-14
Transmit Commands.............................................................................................3-1
Receive Commands ..............................................................................................3-2
Global Error Events ..............................................................................................4-2
SCC Event Register (SCCE) ................................................................................4-3
Interrupt Table Entry ............................................................................................4-5
Channel Interrupt Processing Flow ......................................................................4-7
Receive Buffer Descriptor ....................................................................................5-1
Transmit Buffer Descriptor ..................................................................................5-5
Placement of Buffer Descriptors ..........................................................................5-7
Data Buffer .......................................................................................................2-5
Channel-Specific HDLC Parameters..............................................................2-14
Channel-Specific Transparent Parameters .....................................................2-20
Global Underrun (GUN)...................................................................................4-3
Global Overrun (GOV) in the FIFO.................................................................4-3
Restart from a Global Error..............................................................................4-3
MC68MH360 Internal Memory Structure........................................................5-7
Parameter RAM Usage for QMC over Several SCCs......................................5-9
MPC860MH Internal Memory Structure .......................................................5-14
Freescale Semiconductor, Inc.
CHAMR—Channel Mode Register (HDLC).............................................2-15
TSTATE—Tx Internal State (HDLC)........................................................2-17
INTMSK—Interrupt Mask (HDLC) ..........................................................2-18
RSTATE—Rx Internal State (HDLC) .......................................................2-19
CHAMR—Channel Mode Register (Transparent Mode) ..........................2-21
TSTATE—Tx Internal State (Transparent Mode) .....................................2-23
INTMSK—Interrupt Mask (Transparent Mode)........................................2-24
TRNSYNC—Transparent Synchronization ...............................................2-24
RSTATE—Rx Internal State (Transparent Mode).....................................2-28
For More Information On This Product,
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Buffer Descriptors
QMC Commands
QMC Exceptions
CONTENTS
QMC Supplement
Chapter 3
Chapter 4
Chapter 5
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