MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 85

IC MPU QUICC 33MHZ 357-PBGA

MC68MH360VR33L

Manufacturer Part Number
MC68MH360VR33L
Description
IC MPU QUICC 33MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68MH360VR33L

Processor Type
M683xx 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68MH360VR33L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68MH360VR33LR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
If the QMC operates with a full 64 channels, no space is left in the lower 4-Kbyte area. In
this case, the only free areas are in the RAM pages, each 256-bytes large. Depending on the
functions, channels and protocols used, some areas remain free for buffer descriptors. Also,
if a particular function is not enabled, its parameter RAM area may also be used.
If fewer than 64 logical channels are used or if physical channels are concatenated to super
channels, space is freed in the dual-ported RAM. Each unused logical channel creates a 64-
byte hole in the dual-ported RAM. This area is free for buffer descriptors for any SCC.
QMC channels can also use this space instead of external memory for buffer descriptors,
reducing the load on the external bus.
Figure 5-11 shows the internal memory map for the MPC860MH. Figure 5-12 to
Figure 5-15 show a more detailed memory map for each SCC, showing the parameter RAM
usage for different functions.
Table 5-4 shows the functions available for various protocols on each SCC for the
MPC860MH.
Figure 5-12 to Figure 5-15 show that not all the functions available on each SCC can be
used simultaneously due to overlaps of the register locations stored in the parameter RAM.
SCC1 Yes
SCC2 Yes
SCC3 Yes
SCC4 Yes
• RAM page one is dedicated to SCC1, I
• RAM page two is dedicated for SCC2, SPI, IDMA2 and RISC timers
• RAM page three is dedicated for SCC3, SMC1 and DSP1 operations.
• RAM page four is dedicated for SCC4, SMC2 and DSP2 operations.
No
No
No
No
Available?
Function
Misc, I
IDMA1
SPI, Timer,
IDMA2
SMC1, DSP1
SMC2, DSP2
Transparent
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-4. MPC860MH Functions Available
2
C,
Misc, I
IDMA1
SPI, Timer,
IDMA2
SMC1, DSP1
SMC2, DSP2
Go to: www.freescale.com
Chapter 5. Buffer Descriptors
HDLC
2
C,
Misc, I
IDMA1
SPI, Timer,
IDMA2
SMC1, DSP1
SMC2, DSP2
UART
2
C, IDMA1 and for miscellaneous storage.
2
C,
Misc, IDMA1
I
Timer, IDMA2 Timer, IDMA2 Timer, IDMA2
SPI
DSP1
SMC1
DSP2
SMC2
2
C
Ethernet
Misc, IDMA1
I
SPI
DSP1
SMC1
DSP2
SMC2
2
C
QMC
Misc, IDMA1
I
SPI
DSP1
SMC1
DSP2
SMC2
Shared QMC
2
C

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