MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 13

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

About This Book
This document is a supplement to the MC68360 Quad Integrated Communications
Controller User’s Manual (MC68360UM/AD) and the MPC860 PowerQUICC User’s
Manual (MPC860UM/AD). It replaces the MC68MH360 Reference Manual
(MC68MH360RM/AD).
To locate any published errata or updates for this document, refer to the website at
http://www.mot.com/netcomm.
Audience
This manual is intended for system software and hardware developers. It is assumed that
the reader understands basic concepts of time-division-multiplexed processors and how the
MPC860 CPM operates.
Organization
Following is a summary and a brief description of the major sections of this manual:
• Chapter 1, “Overview,” gives an introduction to the QMC (QUICC multichannel
• Chapter 2, “QMC Memory Organization,” describes the operation specific to the
• Chapter 3, “QMC Commands,” discusses the transmit and receive commands.
• Chapter 4, “QMC Exceptions,” describes QMC interrupt handling.
• Chapter 5, “Buffer Descriptors,” describes the contents of the receive and transmit
• Chapter 6, “QMC Initialization,” discusses the essential steps to initialize QMC
• Chapter 7, “Features Deleted in MC68MH360,” lists the features deleted from the
• Chapter 8, “Performance,” provides a performance table for common configurations
controller) protocol including some example applications.
QMC protocol.
buffer descriptors for the QMC protocol and discusses the placement of QMC and
non-QMC buffer descriptors in internal and external memory.
after a hard reset.
MH360.
supported by the 860MH and/or MH360; covers general guidelines and examples
for determining the serial bit rate and CPM loading on a given system; and discusses
system bus utilization and arbitration.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
About This Book