MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 91

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6
QMC Initialization
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60
This section describes the essential steps to initialize QMC after a hard reset. Section 6.1,
“Initialization Steps,” discusses the steps required to initialize the QMC protocol, and
Section 6.2, “68MH360 T1 Example,” provides example code.
6.1 Initialization Steps
This section describes the steps required to initialize the QMC protocol.
Step 1: Initialize the SIMODE (serial interface mode) register. The SIMODE register is
defined on page 7-78 of the MC68360 User’s Manual, and page 16-114 of the MPC860
user’s manual. Table 6-1 shows the transmit buffer descriptor field descriptions.
SMCx
SMCxCS
SDMx
RFSDx
DSCx
CRTx
STZx
CEx
FEx
GMx
TFSDx
Name
Table 6-1. Transmit Buffer Descriptor Field Descriptions
No. of Bits
Freescale Semiconductor, Inc.
For More Information On This Product,
1
3
2
2
1
1
1
1
1
1
2
Connect to TDM or NMSI
Specify clock source
Normal, echo, or loopback mode
Receive frame sync delay
Double-speed clock (GCI)
Common transmit and receive sync & clk
Set L1TXDx to until serial clks
Clock edge for xmit
Frame sync edge
Grant mode support
Transmit frame sync delay
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Chapter 6. QMC Initialization
Description
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