MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 151

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6
6-14
CYCLE
2
3
4
1
The next example, shown in Figure 6-9, is a read of a misaligned long-word
the second long-word cache entry.
Two read cycles are required for a misaligned long-word operand transfer
from devices that return 32-bit DSACKx encodings. As shown in Figure 6-10,
the first read cycle requests the long word at address $06 and latches the
cycles are also required if STERM is used to indicate a 32-bit port instead of
the 32-bit DSACKx encoding.
operand from devices that return 16-bit DSACKx encodings. The processor
accepts the first portion of the operand, the word from address $06, and
it in the cache also. Finally, the processor accesses the word at $0A to fill
long word at address $04. The second read cycle requests and latches the
long word corresponding to the second cache entry at address $08. Two read
requests a word from address $04 to fill the cache entry. Next, the processor
reads the word at address $08, the second portion of the operand, and stores
LON6 WORD
WORD
WORD
WORD
SIZE
ADDRESS
$OA
$06
$04
$08
$00
Figure 6-9. Single Entry Mode Operation - -
Misaligned Long Word and 16-Bit Port
MC68030 USER'S MANUAL
$04
E E l
$08
~ ]
- FIRST WORD OF OPERANO LATCHED
- TO FILL THE CACHE ENTRY AT$04
- SECOND WORD OF OPERAND
- TO FILL ENTRY AT $08
$OC
COMMENT
MOTOROLA