MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 302

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

SECTION 9
MOTOROLA
vance, but request them by accessing logical addresses. The physical mem-
the needs of programs.
The MC68030 includes a memory management unit (MMU) that supports a
demand-paged virtual memory environment. The memory management is
ory is paged, meaning that it is divided into blocks of equal size called page
frames. The logical address space is divided into pages of the same size. The
The principal function of the MMU is the translation of logical addresses to
contains an address translation cache (ATC) in which recently used logical-
to-physical address translations are stored. As the MMU receives each logical
translation tables in memory for the translation information. The address
transparent translation registers (TT0 and TT1 ) that identify blocks of memory
that can be accessed without translation. The features of the MMU are:
MEMORY MANAGEMENT UNIT
"demand" in that programs do not specify required memory areas in ad-
operating system assigns pages to page frames as they are required to meet
physical addresses using translation tables stored in memory. The MMU
address from the CPU core, it searches the ATC for the corresponding physical
address. When the translation is not in the ATC, the processor searches the
calculations and bus cycles required for this search are performed by micro-
code and dedicated logic in the MC68030. In addition, the MMU contains two
•
• Supports Two-Clock Cycle Processor Accesses to Physical Address Spaces
• Addresses Translated in Parallel with Accesses to Data and Instruction
• On-Chip Fully Associative 22-Entry ATC
• Translation Table Search Controlled by Microcode
• Eight Page Sizes: 256, 512, 1K, 2K, 4K, 8K, 16K and 32K Bytes
• Separate User and Supervisor Translation Table Trees Are Supported
• Two Independent Blocks Can Be Defined as Transparent (Untranslated)
• Multiple Levels of Translation Tables
32-Bit Logical Address Translated to 32-Bit Physical Address with 3-Bit
Caches
Function Code
MC68030 USER'S MANUAL
9-1
9