MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 545

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12
12-20
AS is used to qualify the byte select signals to avoid spurious writes to
memory before the address is valid. During read operations, the read chip
flip-flop. This guarantees that the maximum propagation delay to generate
the TERM signal does not violate the synchronous input hold time of the
when the appropriate byte (or bytes) is being written to as indicated by the
the memory is already enabled with its E input grounded). The last signal
generated by the PAL is the TERM signal. As its equation shows, TERM
the address corresponds to the encoded memory-mapped bank of SRAM.
address decode, which lengthens write operations to three clock cycles. The
signal through two 74F32 OR gates before connecting to the 74F74 D-type
can easily meet the specified data setup time to the SRAMs before the ne-
gation of the write strobes (W). TERM is then connected to the system's
STERM consolidation circuity. The consolidation circuitry should have no
UUCS=/AO */A1 8/RW */A16*/A17*/A18*A30*
UMCS =AO */A1 */RW */A16*/A17*/A18*A30*
SIZ0, SIZ1, AO, and A1 signals. The four signals, UUCS, UMCS, LMCS, and
LLCS, control data bits D24-D31, D16-D23, D8-D15, and D0-D7, respectively.
select (RDCS) signal, qualified with AS, controls the data buffers only (since
consists of two events: one for read cycles and the other for write cycles.
For read cycles, TERM is an address decode signal that is asserted whenever
For write operations, a delayed form of AS (DAS) is used to qualify the same
DAS signal generation is delayed from the clock edge by running the clock
MC68030. By increasing write operation to three clock cycles, the MC68030
more than 15 ns of propagation delay. If the system has no other synchronous
memory or ports, TERM may be connected directly to STERM.
LMCS =/A0 *A1 */RW */A16*/A17*/A18*A30*
LLCS =A0 * A1/RW */A16*/A17*/A18*A30*
RDCS =/A16*/A17*/A18*A3O*RW
DESCRIPTION:
+/A1 * S]ZO * SIZ1 */RW */A16*/A17*/A18*A30*
+/A1 * A0 */SIZ0 */RW */A16*/A17*/A18*A30*
Figure 12-10. Example PAL Equations for Two-Clock Memory Bank
+A0 * SIZ0 *SIZ1 */RW */A16*/A17*/A18*A30*
+/SIZ0 */SIZ1 */RW */A16*/A17*/A18*A30*
+A1 * SIZ1 */RW */A16*/A17*/A18*A30*
+/A15
+/A1 */SIZ0 */SIZ1 */RW */A16*/A17*/A18*A3g*
+/A1 */SIZ0 */RW */A16*/A17*/A18*A30*
+/A1 *SIZ1 */RW */A16*/A17*/A18*A30*
Byte select signals. The byte select signals are asserted only during write operations when the particular byte
being written. The synchronous bank of memory is always enabled, and writes are controlled by W on the memory.
RDCS
/A17 /A18 A30*/RW*DAS
is for buffer control and only asserts for read operations. TERM is the cycle termination signals to the
MC68030 USER'S MANUAL
;directly addressed, any
;directly addressed, any
;word aligned, size is word or long word
;directly addressed, any size
;word aligned, size is long word
;word aligned, size is three byte
;word aligned, size is word or long word
;size is long word, any address
;immediate STERM with proper address
;word aligned, size byte or three byte
;directly addressed, any size
;odd alignment, three byte
;word aligned, word or three byte size
;write Cycles take three clocks
size
size
size
MOTOROLA
MC68030.
is