MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 44

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
1.7
T H E M E M O R Y
The MMU supports virtual memory systems by translating logical addresses
to physical addresses using translation tables stored in memory. The MMU
stores address mappings in an address translation cache (ATC) that contains
the most recently used translations. When the ATC contains the address for
a bus cycle requested bythe CPU, a translation table search is not performed.
The memory management function performed by the MMU is called demand
the access causes a demand for the operating system to load or allocate the
ory management because physical memory is managed in blocks of a spec-
Features of the MMU include:
paged memory management. Since a task specifies the areas of memory it
requires as it executes, memory allocation is supported on a demand basis.
If a requested access to memory is not currently mapped by the system, then
required memory image. The technique used by the MC68030 is paged mem-
ified number of bytes, called page frames. The logical address space is divided
• Address Translations and Internal Instruction and Data Cache Accesses
• Two Optional Transparent Blocks
• Used and Modified Bits Automatically Maintained in Tables and ATC
•
•
• Multiple Level Translation Tables with Short- and Long-Format Descrip-
• Table Searches Automatically Performed in Microcode
• 22-Entry Fully Associative ATC
• Eight Page Sizes Available Ranging from 256 to 32K Bytes
• User and Supervisor Root Pointer Registers
• Write Protection and Supervisor Protection Attributes
• Translations Enabled/Disabled by Software
• Translations Can Be Disabled with External MMUDIS Signal
• Cache Inhibit Output (CLOUT) Signal Can Be Asserted on a Page-by-Page
•
tors for Efficient Table Space Usage
32-Bit Internal Logical Address with Capability To Ignore as many as 15
3-Bit Function Code Supports Separate Address Spaces
32-Bit Physical Address
Performed in Parallel
Basis
Upper Address Bits
M A N A G E M E N T
MC68030 USER'S MANUAL
U N I T
1-15
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