MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 317

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9
9.3 TRANSPARENT TRANSLATION
9-16
Two independent transparent translation registers (TTO and TT1 ) in the MMU
translated to the physical address spaces. The MMU does not explicitly check
write protection for the addresses in these blocks, but a block can be specified
TTx registers include at least 16M bytes of logical address space; the two
The following description of the address comparison assumes that both TTO
When the MMU receives an address to be translated, the function code and
the eight high-order bits of the address are compared to the block of ad-
field is set, the corresponding bit of the base function code or logical base
successively higher order bits in the address mask increases the size of the
transparently translated block.
The address for the current bus cycle and a TTx register address match when
the function code bits and address bits (not including masked bits) are equal.
write) can also be masked. The read/write mask bit (RWM) must be set for
transparent translation of addresses used by instructions that execute read-
ters, regardless of the function code and address bits for the individual cycles
within a read-modify-write operation.
translation does not become effective until the entire transfer is complete.
transparent translation registers.
optionally define two blocks of the logical address space that are directly
as transparent only for read cycles. The blocks of addresses defined by the
blocks can overlap, or they can be separate.
and TT1 are enabled; however, each TTx register can be independently dis-
abled. A disabled TTx register is completely ignored.
dresses defined by TTO and TT1. The address space block for each TTx
register is defined by the base function code, the function code mask, the
logical base address, and the logical address mask. When a bit in a mask
address is ignored in the function code and address comparison. Setting
Each TTx register can specify read accesses or write accesses as transparent.
In that case, the internal read/write signal must match the R/W bit in the TTx
register for the match to occur. The selection of the type of access (read or
modify-write operations. Otherwise, neither the read nor write portions of
if MMUDIS is asserted during this type of operation, the disabling of address
read-modify-write operations are mapped transparently with the TTx regis-
Note that the assertion of MMUDIS does not affect the operation of the
MC68030 USER'S MANUAL
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