MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 259

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Im
7-98
7.7.1 Bus Request
1) ASSERT BUS GRANT (~)
1) NEGATE B'6 AND WAIT FOR DOACK TO 8E NEGATED
serting DR. This can be a wire-ORed signal (although it need not be con-
structed from open-collector devices) that indicates to the processor that
some external device requires control of the bus. The processor is effectively
at a lower bus priority level than the external device and relinquishes the
ordinary processing if the arbitration circuitry inadvertently responds to noise
External devices capable of becoming bus masters request the bus by as-
bus after it has completed the current bus cycle (if one has started).
If no acknowledge is received while the BR is active, the processor remains
bus master once BR is negated. This prevents unnecessary interference with
or if an external device determines that it no longer requires use of the bus
before it has been granted mastership.
RE-ARBITRATE OR RESUME PROCESSOR OPERATION
GRANT BUS ARBITRATION
TERMINATE ARBITRATION
Figure 7-59. Bus Arbitration Flowchart for Single Request
PROCESSOR
MC68030 USER'S MANUAL
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1
2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE
3) NEXT BUS MASTER ASSERTS BUS GRANT ACKNOWLEDGE (BGACK)
4) BUS MASTER NEGATES
1) NEGATE BGACK
1) ASSERT BUS REQUEST (~)
1) EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER
1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES)
TO BECOME NEW MASTER
ACKNOWLEDGE BUS MASTERSHIP
RELEASE BUS MASTERSHIP
OPERATE AS BUS MASTER
REQUESTING DEVICE
REQUEST THE BUS
+
MOTOROLA