MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 469

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

11
11-6
11.3 INSTRUCTION EXECUTION TIMING CALCULATIONS
11.3. 1 Instruction-Cache Case
11.2.6 Memory Management Unit
translations. When the physical address corresponding to a logical address
with on-chip cache accesses and has no effect on instruction timing.
When the ATC does not contain the translation for a logical address, the
translation tree and whether a nonresident portion of the translation tree is
The MMU supports demand-paged virtual memory. When a table search
terminates with an exception, indicating that therequested instruction or
data is not resident, additional time to bring the appropriate page into mem-
ory is required. The time required is dependent on the handling routine for
the exception.
The instruction-cache-case timing, overlap, average no-cache-case timing,
and actual instruction-cache-case execution time calculations are discussed
The instruction-cache-case (CC) time for an instruction is the total number
sponding instruction prefetches are resident in the on-chip instruction cache.
All bus cycles are assumed to take two clock periods. The instruction-cache-
case time does not assume any overlap with other instructions nor does it
take into account hits in the on-chip data cache. The overall instruction-cache-
time for the required effective address calculation (CCea) and the instruction-
tables of 11.6
The MC68030 includes a memory management unit (MMU) that translates
The MMU uses an address translation cache (ATC) to store recently used
processor performs a table search operation to external memory. The amount
of time required for a table search depends on the structure of the address
required.
in the following paragraphs.
of clock periods required to execute the instruction, provided all the corre-
case time for some instructions is divided into the instruction-cache-case
cache-case time for the remainder of the operation (CCop). The instruction-
cache-case times for all instructions and addressing modes are listed in the
logical addresses to physical addresses for external accesses when required.
resides in the ATC, the address translation time is completely overlapped
I N S T R U C T I O N T I M I N G TABLES.
MC68030 USER'S MANUAL
MOTOROLA