MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 149
MC68030CRC33C
Manufacturer Part Number
MC68030CRC33C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030CRC33C
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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6
6-12
p o r t size is 32 bits, the processor performs two accesses, one for each cache
With a 32-bit port, the same operation is shown in Figure 6-7. Only one read
cycle is required. All four bytes (including the requested byte) are latched
during the cycle.
controller attempts to fill both associated long-word cache entries. An ex-
The MC68030 first fetches the initial byte(s) of the operand (residing in the
first long word} and then requests the remaining bytes to fill that cache entry
If a requested access is misaligned and spans two cache entries, the bus
ample of this is an operand request for a long word on an odd-word boundary.
(if the port size is less than 32 bits) before it requests the remainder of the
operand and corresponding long word to fill the second cache entry. If the
entry.
CYCLE
CYCLE
2
1
WORD
BYTE
BYTE
SIZE
SIZE
Figure 6-6. Single Entry Mode Operation - - 16-Bit Port
Figure 6-7. Single Entry Mode Operation - - 32-Bit Port
ADDRESS
ADDRESS
$03
$00
$03
SOD
$00
MC68030 USER'S MANUAL
11111
$04
$04
- INCLUDES THE REQUESTED OPERAND AND THE PREVIOUS BYTE
- THE REMAINING WORD FOR THE LONG WORD CACHE ENTRY
- THE ENTIRE LONG WORD MUST BE VALID
$08
$08
COMMENT
COMMENT
$OC
$0C
MOTOROLA
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