MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 393
MC68030CRC33C
Manufacturer Part Number
MC68030CRC33C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030CRC33C
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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10.1.4.2 PROCESSOR-COPROCESSOR INTERFACE.
10-6
To improve the efficiency of operand transfers between memory and the
sor provides all control, address, and data signals necessary to request and
obtain the bus and then performs DMA transfers using the bus. DMA copro-
of the signals involved in an asynchronous non-DMA M68000 coprocessor
A13-A15 of the address bus is used with other address signals to select the
coprocessor, the system designer can use several coprocessors of the same
type and assign a unique CplD to each one.
coprocessor, a coprocessor that requires a relatively high amount of bus
bandwidth or has special bus requirements can be implemented as a DMA
coprocessor. DMA coprocessors can operate as bus masters. The coproces-
cessors, however, must still act as bus slaves when they require information
or services of the main processor using the M68000 coprocessor interface
protocol.
interface. The synchronous interface is similar. Since the CplD on signals
MAIN PROCESSOR
Figure 10-2. Asynchronous Non-DMA M68000 Coprocessor
MC68030
*Chip select logic may be integrated into the coprocessor
Address lines not specified above are "0" during coprocessor access
AIg-A16 = 0010 ~
A15-A13 = xxx
A4-A1 = rrrr
FCO-FC2 = 111
t
A19-A13
R ~
A4-A1
FCO-FC2
031~D0
MC68030 USER'S MANUAL
~
~
~
Interface Signal Usage
/ =
/
CPU SPACE CYCLE
COPROCESSOR ACCESS IN CPU SPACE
COPROCESSOR IDENTIFICATION
COPROCESSOR INTERFACE REGISTER SELECTOR
COPROCESSOR
/
/
t
(
DECODE
LOGIC*
~ / D S - - ~
Figure 10-2 is a block diagram
==
ASYNCHRONOUS
iNTERFACE
COPROCESSOR
LOGIC
BUS
MOTOROLA
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