MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 523

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

11.7.2 MMU Instruction Timing
11-60
The MMU instruction timing table lists the numbers of clock periods needed
for the MMU to perform the MMU instructions. The total number of clock
cycles is outside the parentheses. It includes the numbers of read, prefetch,
and write cycles, which are shown inside the parentheses as (r/pr/w).
NOTES:
***Number given is the maximum for a six-level table (FC lookup, a, b, c, and d levels with indirect level, all long
PMOVE (from CRP, SRP)*
PMOVE (to CRP, SRP, valid)*
PMOVE (to CRP, SRP, invalid) 1.
PMOVE (from TT0, TT1)*
PMOVE (to TT0, TT1)*
PMOVE (from MMUSR)*
PMOVE (to MMUSR)*
PMOVE (from TC)*
PMOVE (to TC, valid) 2.
PMOVE (to TC, invalid) 3.
PMOVE (to TC) 4.
PFLUSHA
PFLUSH <fc),#(mask> (fc is immediate or data register)
PFLUSH <fc),#<mask) (fc is in SFC or DFC register)
PFLUSH <fc>,#<mask>,<ea> (fc is immediate or data register)*
PFLUSH <fc),#(mask>,<ea) (fc is in SFC or DFC register)*
PLOAD[R:W] <fc),<ea> (fc is immediate or data register)**
PLOAD[R:W] <fc>,(ea> (fc is in SFC or DFC register)**
PTEST[R:W] <fc>,<ea),#6 * * * *
PTEST[R:W] <fc>,<ea),#0*
**Add the appropriate effective address calculation time and the table search time.
4. Translation disabled.
1. Attempt to load invalid root pointer.
2. Translation enabled.
3. Number is maximum, assuming valid page size but TIx fields do not add up to 32. Translation enabled.
*Add the appropriate effective address calculation time.
descriptors).
Instruction
MC68030 USER'S M A N U A L
Head
0
0
0
0
0
2
0
2
0
0
0
0
0
0
0
0
0
0
0
0
Tail
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I-CacheCase No-CacheCase
28(3/0/4)
38(1/0/0)
56(2/0/4)
20(0/0/0)
20(0/0/0)
22(0/0/0)
12(2/0/0)
12(1/0/0)
14(1/0/0)
12(0/0/0)
16(0/0/0)
16(0/0/0)
12(0/0/0)
88(12/0/0)
4(0/0/2)
8(0/0/1)
4(0/0/1)
6(1/0/0)
4(0/0/1)
8(0/0/0)
M O T O R O L A
88(12/1/0)
30(3/2/4)
40(1/2/0)
58(2/2/4)
22(0/2/0)
22(0/2/0)
22(0/1/0)
14(2/2/0)
14(1/2/0)
16(1/2/0)
14(0/2/0)
18(0/2/0)
18(0/2/0)
10(0/2/0)
14(0/2/0)
5(0/1/2)
8(0/1/1)
5(0/1/1)
6(1/1/0)
5(0/1/1)