MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 170

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
Table 7-4 lists the bytes required on the data bus for read cycles that are
that are read or written during that bus cycle and are defined by SIZO, SlZl,
AO, and A1 for the bus cycle. The PRn and the Nn bytes correspond to the
cachable. The entries shown as OPn are portions of the requested operand
previous and next bytes in memory, respectively, that must be valid on the
data bus for the specified port size (long word or word) so that the internal
caches operate correctly. (For cachable accesses, the MC68030 assumes that
all portions of the data bus for a given port size are valid.) This same table
applies to noncachable read cycles except that the bytes labeled PRn and Nn
are not required and can be replaced by "don't cares".
ADDRESSES
. . . . .
I N C R E A S I N G
SIZ1
Table 7-2. Size Signal
0
0
1
1
MULTIPLEXER
EXTERNAL __[
DATA BUS
REGISTER I
ADDRESS
xxxxxxxO
xxxxxxxO
Encoding
Figure 7-4. MC68030 Interface to Various Port Sizes
SIZO
2
2
3
1
0
0
1
1
I
I
a
B31-D24
B Y T E O
B Y T E
BYTE O
BYTE 1
BYTE2
BYTE 3
Word
Byte
3 Bytes
Long Word
0PO
I
\
MC68030 USER'S MANUAL
2
Size
J
B-BIT PORT
ROUTING
D23-D16
B Y T E |
B Y T E 3
0P1
\
AND OUPUC~ON
16-81"i " PORT
g;5-gB
0P2
/
Table 7-3. Address Offset
A1
0
0
1
1
l
D7-DO
0P3
~
/,
Encodings
I
A0
O
0
1
1
+0 Bytes
+ 1 Byte
+ 2 Bytes
+ 3 Bytes
EXTERNAL BUS
Offset
~,
7-9
7