MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 524

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
11.8 Interrupt Latency
ance. Processors in the M68000 Family support asynchronous assertion of
The average interrupt latency is quite short, but the maximum latency is
than the maximum interrupt latency. The maximum interrupt latency for the
with a bus error), but when the MMU is enabled, some operations can take
several times longer to execute.
time of main memory, and the width of the data bus connecting the MC68030
to main memory. It is important to note that the address translation tree
configuration is under software control and can strongly affect the system
the code and data items crossing page boundaries. The assembler syntax
for this instruction is:
This instruction can cause ten address translation tree searches: two for the
word boundaries, the indirect address and operands can cause only one
translation search each. This reduces the number of searches for the instruc-
tion to a maximum of six.
In real-time systems, the response time required for a processor to service
an interrupt is a very important factor pertaining to overall system perform-
interrupts and begin processing them on subsequent instruction boundaries.
often critical because real-time interrupts cannot require servicing in less
MC68030 alone is approximately 200 clock cycles (for the MOVEM.L
([d32,An],Xn,d32), D0-D7/A0-A7 instruction where the last data fetch is aborted
Interrupt latency in systems using the MMU is affected by the length of the
main processor instructions, the address translation tree configuration, the
number of translation tree searches required by the instructions, the access
interrupt latency. The maximum interrupt latency for a given system config-
uration can be computed by adding the length of the longest main processor
instruction to the time required for the maximum number of translation tree
searches that the instruction could require. For the MC68030 microprocessor,
one instruction of particular interest is a memory-to-memory move with
memory indirect addressing for both the source and destination, with all of
instruction stream, two for the sou rce indirect address, two for the destination
indirect address, two for the operand fetch, and two for the destination write.
System software can reduce the maximum number of translation searches
by placing additional restrictions on generated code. For example, if the
language translators in the system only generate long words aligned on long-
MOVE.L (od,[bd,An,Rm]),(od,[bd,An,Rm])
MC68030 USER'S MANUAL
11-61
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