MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 567
MC68030CRC33C
Manufacturer Part Number
MC68030CRC33C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030CRC33C
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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12
12-42
The processor halt (PHALT) signal indicates that the MC68030 has received
The FILL signal indicates a break in sequential instruction execution. FILL is
The sample signal (SAMPLE) is an active-high signal which qualifies the next
falling edge of the CLK signal as the sampling point. Five types of conditions
cause SAMPLE to assert:
The remaining five output signals are used to qualify the information col-
a double bus fault and needs a reset operation to continue processing. PHALT
asserts after the assertion of STATUS for greater than three clock cycles and
generates a SAMPLE signal.
a latched version of the REFILL signal and remains asserted until a sample
does not generate a SAMPLE signal.
The exception pending (EP) signal indicates that the MC68030 is beginning
cache miss, trace exception, or interrupt exception. The EP signal asserts
tion of EP does generate a SAMPLE signal.
lected.
is collected as indicated by the assertion of SAMPLE. The assertion of FILL
exception processing for either a reset, bus error, address error, spurious
interrupt, autovectored interrupt, F-line instruction, MMU address translation
after STATUS negates from a two- or three-clock cycle assertion. The asser-
2. An internal cache hit, including a hit in the cache holding register
3. An instruction boundary
4. Exception processing as marked by the EP signal discussed below
5. The processor halting
1. An external bus cycle
Quantity
2
1
1
1
74F00
74F74
74F114
PAL16R6D Programmable Logic Array, Ultra High Speed
MC68030 USER'S MANUAL
Part
Table 12-5. List of Parts
Dual JK Negative Edge-Triggered Flip-Flop
Quad 2 Input NAND Gate
Dual D-Type Positive Edge-Triggered Flip-Flop
Part
Description
MOTOROLA
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