MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 359
MC68030CRC33C
Manufacturer Part Number
MC68030CRC33C
Description
IC MPU 32BIT ENHANCED 128-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68030CRC33C
Processor Type
M680x0 32-Bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
128-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
33MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
128
Package Type
PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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Read/Write (R/W)
Read/Write Mask (RWM)
Function Code Base (FC BASE)
Function Code Mask (FC MASK)
LOGICAL ADDRESS BASE
Cache Inhibit (Cl)
This bit defines the type of access that is transparently translated (for a
This bit masks the R/W field:
When RWM is set to one, both read and write accesses of a matching
the RWM bit equals zero, neither the read nor the write of any read-modify-
write cycle is transparently translated with the TTx register.
This 3-bit field defines the base function code for accesses to be trans-
translated.
This 3-bit field contains a mask for the FC BASE field. Setting a bit in this
field causes the corresponding bit of the FC BASE field to be ignored.
This 8-bit field is compared with address bits A31-A24. Addresses that
translated.
This bit inhibits caching for the transparent block:
When this bit is set, the contents of a matching address are not stored in
the internal instruction or data cache. Additionally, the cache inhibit out
signal (CLOUT) is asserted when this bit is set, and a matching address is
matching address):
address are transparently translated. For transparent translation of read-
parently translated with this register. Addresses with function codes that
match the FC BASE field (and are otherwise eligible) are transparently
accessed, signaling external caches to inhibit caching for those accesses.
modify-write cycles with matching addresses, RWM must be set to one. If
match in this comparison (and are otherwise eligible) are transparently
0 - - Write accesses transparent
0 - - R/W field used
0 - - Caching allowed
1 - - Read accesses transparent
1 - - Caching inhibited
1 - - R/W field ignored
MC68030 USER'S MANUAL
MOTOROLA
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