MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 94

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

M O T O R O L A
3 . 2 . 6 Bit Field I n s t r u c t i o n s
NOTE: All bit field instructions set the N and Z bits as shown for BFTST before performing the specified operation.
The MC68030 supports variable-length bit field operations on fields of up to
to the bit manipulation operations; bit field test (BFTST), bit field test and
32 bits. The bit field insert (BFINS) instruction inserts a value into a bit field.
extract a value from the field. Bit field find first one (BFFFO) finds the first
set (BFSET), bit field test and clear (BFCLR), and bit field test and change
Bit field extract unsigned (BFEXTU) and bit field extract signed (BFEXTS)
bit that is set in a bit field. Also included are instructions that are analogous
(BFCHG). Table 3-6 is a summary of the bit field
BFCHG
BFCLR
BFEX-I'S
BFEXTU
BFFFO
BFINS
BFSET
BFTST
Instruction
BCHG
BCLR
BSET
BTST
Instruction
{ea} {offset:width/,Dn
(ea) {offset:width},Dn
Dn,(ea) {offset:width}
{ea), toffset:width},Dn
(ea~ {offset:width}
(ea) {offset:width}
{ea) {offset:width}
(ea) {offset:width}
Operand Syntax
Operand Syntax
#(data),(ea)
#(data),{ea)
#(data),(ea)
#(data),(ea)
Dn,<ea)
Dn,{ea)
Dn,(ea~
Dn,(ea)
Table 3-5. Bit Mani
Table 3-6. Bit Field Operations
M C 6 8 0 3 0 U S E R ' S M A N U A L
Operand Size
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
Operand Size
1-32
1-32
1-32
1-32
1-32
1-32
1-32
1-32
: - ((bit number) of destination) t Z;
3 u l a t i o n
~ ((bit number> of destination) i Z;
~ ((bit number) of destination) I Z
- ({bit number) of destination) ~ Z i bit of destination
1 i bit of destination
i - Field 0 Field
!0's i Field
I I's ~ Field
! Field MSB J) N; - (OR of all bits in field) J) Z
0 ~ bit of destination
Scan for first bit set in field; offset 0 Dn
F;eid ~ Dn; Sign Extended
Field t Dn; Zero Extended
Dn J) Field
O p e r a t i o n s
operations.
Operation
Operation
3-9