MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 261

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7.7.3 Bus Grant Acknowledge
7.7.4 Bus Arbitration Control
7-100
When BGACK is asserted, the device isthe bus master until it negates BGACK.
ternal bus cycles before it reasserts BG in this case.
The bus arbitration control unit in the MC68030 is implemented with a finite
As shown in Figure 7-61, input signals labeled R and A are internally syn-
T is true, the address, data, and control buses are placed in the high-
tion that follows the protocol.
General-purpose devices are then connected to be dependent only on AS.
BGACK should not be negated until all bus cycles required by the alternate
bus master are completed. Bus mastership terminates at the negation of
asserted. If a BR is still pending after the assertion of BGACK, another BG is
asserted within a few clocks of the negation of BG, as described in the 7.7.4
Bus Arbitration Control,
state machine. As discussed previously, all asynchronous inputs to the
processor Clock.
ch ronized versions of the BR and BGACK signals, respectively. The BG output
is labeled G, and the internal high-impedance control signal is labeled T. If
impedance state after the next rising edge following the negation of AS and
true active voltage level.
BG may be routed through a daisy-chained network or through a specific
priority-encoded network. The processor allows any type of external arbitra-
chronous termination, STERM), and BGACK are negated before asserting its
own BGACK. The negation of the AS indicates that the previous master
trica/Spec/f/cations). The negation of [)SACKx or STERM indicates that the
previous slave has completed its cycle with the previous master. Note that
in some applications, DSACKx might not be used in this way.
BGACK. The BR from the granted device should be negated after BGACK is
MC68030 are internally synchronized in a maximum of two cycles of the
RMC. All signals are shown in positive logic (active high), regardless of their
Upon receiving BG, the requesting device waits until AS, DSACKx (or syn-
releases the bus after specification #7 (refer to MC68030EC/D, MC68030 Elec-
MC68030 USER'S MANUAL
Note that the processor does not perform any ex-
MOTOROLA