MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 193

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-32
4) DRIVE FUNCTION CODE ON FCO-FC2
2) SET R/WTO READ
3) DRIVE ADDRESS ON AO-A31
4) DRIVE FUNCTION CODE ON FCO-FC2
5) DRIVE SIZE (SIZO-SIZ1) (FOUR BYTES)
6) CACHE INHIBIT OUT (CLOUT) BECOMES VALID
7) ASSERT ADDRESS STROBE ( ~ )
8) ASSERT DATA STROBE (O'S)
9) ASSERT DATA BUFFER ENABLE (DBEN)
2) LATCH DATA
31 NEGATE AS AND DS
4) NEGATE DBEN
2) SET R/WTO READ
3) DRIVE ADDRESS ON AO-A3"
5) DRIVE SIZE fSIZO-SlZll lONE BYTE)
6) CACHE INHIBIT OUT (CLOUT1 BECOMES VAUD
7) ASSERT ADDRESS STROBE IA'S~
81 ASSERT DATA STROBE (D'S)
9) ASSERT DATA BUFFER ENABLE (DBEN)
2t LATCH DATA
31 NEGATE AS AND OS
4~ NEGATE DBEN
1) ASSERT ECS/OCS FOR ONE-HALF CLOCK
1) SAMPLE CACHE INHIBIT IN (CIIN)
II ASSERT ECS/OCS FOR ONE-HALF CLOCK
1 SAMPLE CACHE INHIBIT IN (CIIN)
Figure 7-19. Asynchronous Long-Word Read Cycle Flowchart
Figure 7-20. Asynchronous Byte Read Cycle Flowchart
START NEXT CYCLE
START NEXT CYCLE
ADDRESS DEVICE
ADDRESS DEVICE
ACQU RE DATA
ACQUIRE DATA
PROCESSOR
PROCESSOR
MC68030 USER'S MANUAL
L
1
2) PLACE DATA ON DO-D31
3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx)
1) DECODE ADDRESS
1) REMOVE DATA FROM DO-D31
2) NEGATE DSACKx
2) PLACE DATA ON D31-D24 OR
3) ASSERT DATA TRANSFER AND SIZE ACKNOWLEDGE (DSACKx)
1) DECODE ADDRESS
1) REMOVE DATA FROM DATA BUS
2) NEGATE DSACKx
(BASED ON AO, A].CACHE, AND BUS WIDTH)
D23-D16 OR
D15-D8 DR
D7-DO
EXTERNAL DEVICE
TERMINATE CYCLE
TERMINATE CYCLE
EXTERNAL DEVICE
PRESENT DATA
PRESENT DATA
MOTOROLA