MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 20

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
Number
7-25
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7-20
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7 - 2 3
7-24
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7-28
Figure
Asynchronous Byte and Word Read Cycles - - 32-Bit Port ........
Asynchronous Write Cycle Flowchart .....................................
Asynchronous Read-Write-Read Cycles - - 32-Bit Port ..............
Asynchronous Byte and Word Write Cycles - - 32-Bit Port ........
Asynchronous Read-Modify-Write Cycle Flowchart ....... i ..........
Asynchronous Byte Read-Modify-Write Cycle - - 32-Bit Port
Autovector Operation Timing ................................................
Asynchronous Byte Read Cycle Flowchart ..............................
Long-Word Operand Write - - 8-Bit Port .................................
Synchronous Long-Word Read Cycle F l o w c h a r t - No Burst
Synchronous Read with CIIN Asserted and CBACK Negated .....
Synchronous Write Cycle Flowchart .......................................
Synchronous Write Cycle with Wait States - - CLOUT Asserted
Synchronous Read-Modify-Write Cycle Flowchart ...................
Synchronous Read-Modify-Write Cycle Timing - - CIIN
Burst Operation Flowchart - - Four Long Words Transferred .....
Long-Word Operand Request from $07 with Burst Request
Long-Word Operand Request from $07 with Burst
Long-Word Operand Request from $07 with Burst
Interrupt Acknowledge Cycle Flowchart ..................................
Interrupt Acknowledge Cycle Timing ......................................
Breakpoint Operation Flow ...................................................
Breakpoint Acknowledge Cycle Timing (Exception Signaled) ....
Bus Error without DSACKx ...................................................
Late Bus Error with DSACKx .................................................
Late Bus Error with STERM - - Exception Taken ......................
Long-Word Read - - 8-Bit Port with CLOUT Asserted ................
Long-Word Read - - 16-Bit and 32-Bit Port ..............................
Long-Word Operand Write - - 16-Bit Port ................................
Long-Word Operand Request from $0E - - Burst Fill Deferred...
MC68030 CPU Space Address Encoding .................................
Breakpoint Acknowledge Cycle Timing ......................... :. ........
Allowed .......................................... .................................
Asserted ..........................................................................
and Wait Cycles ................................................................
Request - - CBACK Negated Early
(TAS Instruction with CLOUT or CIIN Asserted) .....................
Request - - CBACK and ClIN Asserted .................................
,LIST OF ILLUSTRATIONS (Continued)
MC68030 USER'S MANUAL
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