DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 22

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Signal Name:
Signal Description:
Signal Type:
A 4kHz to 20kHz clock for the RLINK output. Used for sampling Sa bits. This signal is not bonded out in
the DS21FF44/DS21FT44.
Signal Name:
Signal Description:
Signal Type:
2.048MHz clock that is used to clock data through the receive side framer.
Signal Name:
Signal Description:
Signal Type:
A 256kHz clock that pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when
FMS = 1 (DS21Q43 emulation). This signal is not bonded out in the DS21FF44/DS21FT44.
Signal Name:
Signal Description:
Signal Type:
A user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384kbps service,
768kbps, or ISDN–PRI. Also useful for locating individual channels in drop-and-insert applications, for
external per-channel loopback, and for per-channel conditioning. See Section 16 for details.
Signal Name:
Signal Description:
Signal Type:
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide, is output at this pin, which identifies either frame or CAS/CRC
multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an
input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.
Signal Name:
Signal Description:
Signal Type:
An extracted 8kHz pulse, one RCLK wide, is output at this pin, which identifies frame boundaries. This
signal is not bonded out in the DS21FF44/DS21FT44.
RLCLK
Receive Link Clock
Output
RCLK
Receive Clock Input
Input
RCHCLK
Receive Channel Clock
Output
RCHBLK
Receive Channel Block
Output
RSER
Receive Serial Data
Output
RSYNC
Receive Sync
Input /Output
RFSYNC
Receive Frame Sync
Output
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