DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 71

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 19-1. HDLC CONTROLLER REGISTER LIST
HDLC Control Register (HCR)
HDLC Status Register (HSR)
HDLC Interrupt Mask Register (HIMR)
Receive HDLC Information Register
(RHIR)
Receive HDLC FIFO Register (RHFR)
Receive HDLC DS0 Control Register 1
(RDC1)
Receive HDLC DS0 Control Register 2
(RDC2)
Transmit HDLC Information Register
(THIR)
Transmit HDLC FIFO Register (THFR)
Transmit HDLC DS0 Control Register 1
(TDC1)
Transmit HDLC DS0 Control Register 2
(TDC2)
19.2. HDLC Status Registers
Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a
particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be
set to a one. Some of the bits in these three status registers are latched and some are real time bits that are
not latched. Section 19.4 contains register descriptions that list which bits are latched and which are not.
With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads
that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred
again. The real time bits report the current instantaneous conditions that are occurring and the history of
these bits is not latched.
Like the other status registers in the framer, the user will always proceed a read of any of the three
registers with a write. The byte written to the register will inform the framer which of the latched bits the
user wishes to read and have cleared (the real time bits are not affected by writing to the status register).
The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read
and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with current value and it will be cleared. When a
zero is written to a bit position, the read register will not be updated and the previous value will be held.
A write to the status and information registers will be immediately followed by a read of the same
NAME
Key status information for both transmit and receive
Allows/stops status bits to/from causing an interrupt
General control over the HDLC controller
directions
Status information on receive HDLC controller
Access to 64-byte HDLC FIFO in receive direction
Controls the HDLC function when used on DS0 channels
Status information on transmit HDLC controller
Access to 64–byte HDLC FIFO in transmit direction
Controls the HDLC function when used on DS0 channels
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FUNCTION
DS21FT44/DS21FF44