DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 61

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC. There are no restrictions on which channels can be looped back or on how many channels can
be looped back.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address = 26 to 29 Hex)
(Also used for Per-Channel Loopback)
Note: If CCR3.5 = 1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a
one implies that channel data is to be sourced from the output of the receive side framer (i.e., Per-Channel
Loopback; see Figure 6–1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex)
15.1.2.
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8-bit code
to be placed into each of the 32 E1 channels.
(MSB)
CH16
CH24
CH32
(MSB)
TIDR7
CH8
SYMBOL
SYMBOL
CH1 –32
TIDR7
TIDR0
Per-Channel Code Insertion
CH15
CH23
CH31
CH7
TIDR6
POSITION
POSITION
TIR1.0–4.7
CH14
CH22
CH30
CH6
TIDR.7
TIDR.0
TIDR5
CH13
CH21
CH29
CH5
Transmit Idle Code Insertion Control Bits
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
TIDR4
CH12
CH20
CH28
CH4
61 of 117
TIDR3
NAME AND DESCRIPTION
NAME AND DESCRIPTION
CH11
CH19
CH27
CH3
TIDR2
CH10
CH18
CH26
CH2
(LSB)
CH17
CH25
TIDR1
CH1
CH9
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
TIDR0
(LSB)