DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 81

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address = BB Hex)
20.
In many architectures, the outputs of individual framers are combined into higher speed serial buses to
simplify transport across the system. The DS21Q44 can be configured to allow each framer’s data and
signaling busses to be multiplexed into higher speed data and signaling busses eliminating external
hardware saving board space and cost.
The interleaved PCM bus option supports two bus speeds and interleave modes. The 4.096MHz bus
speed allows two framers to share a common bus. The 8.192MHz bus speed allows all four of the
DS21Q44’s framers to share a common bus. Framers can interleave their data either on byte or frame
boundaries. Framers that share a common bus must be configured through software and require several
device pins to be connected together externally (Figures 20-1 and 20-2). Each framer’s elastic stores must
be enabled and configured for 2.048MHz operation. The signal RSYNC must be configured as an input
on each framer.
For all bus configurations, one framer will be configured as the master device and the remaining framers
on the shared bus will be configured as slave devices. Refer to the IBO register description below for
more detail. In the 4.096MHz bus configuration there is one master and one slave per bus. Figure 20-1
shows the DS21Q44 configured to support two 4.096 MHz buses. Bus 1 consists of framers 0 and 1. Bus
2 consists of framers 2 and 3. Framers 0 and 2 are programmed as master devices. Framers 1 and 3 are
programmed as slave devices. In the 8.192 MHz bus configuration there is one master and three slaves.
Figure 20-2 shows the DS21Q44 configured to support an 8.192MHz bus. Framer 0 is programmed as the
master device. Framers 1, 2, and 3 are programmed as slave devices. Consult timing diagrams in section
22 for additional information.
When using the frame interleave mode, all framers that share an interleaved bus must have receive signals
(RPOS and RNEG) that are synchronous with each other. The received signals must originate from the
same clock reference. This restriction does not apply in the byte interleave mode.
(MSB)
TDB8
SYMBOL
TDB8
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
TDB1
INTERLEAVED PCM BUS OPERATION
TDB7
POSITION
TDC2.7
TDC2.6
TDC2.5
TDC2.4
TDC2.3
TDC2.2
TDC2.1
TDC2.0
TDB6
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to
stop this bit from being used.
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to
stop this bit from being used.
TDB5
81 of 117
TDB4
NAME AND DESCRIPTION
TDB3
TDB2
(LSB)
TDB1