DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 72

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

register. The read result should be logically AND’ed with the mask byte that was just written and this
value should be written back into the same register to insure that bit does indeed clear. This second write
step is necessary because the alarms and events in the status registers occur asynchronously in respect to
their access by the parallel port. This write-read-write (for polled-driven access) or write–read (for
interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS21Q44 with higher order software languages.
Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware
interrupt by the INT* output pin. Each of the events in the HSR can be either masked or unmasked from
the interrupt pin by the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low
when the event occurs. The INT* pin will be allowed to return high (if no other interrupts are present)
when the user reads the event bit that caused the interrupt to occur.
19.3. BASIC OPERATION DETAILS
As a basic guideline for interpreting and sending HDLC messages, the following sequences can be
applied:
Receive a HDLC Message
1) Enable RPS interrupts.
2) Wait for interrupt to occur.
3) Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt.
4) Read RHIR to obtain REMPTY status.
5) Repeat Step 4.
6) Wait for interrupt, skip to Step 4.
7) If POK = 0, then discard whole packet, if POK = 1, accept the packet.
8) Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to Step 1.
Transmit a HDLC Message
1) Make sure HDLC controller is done sending any previous messages and is current sending flags by
2) Enable either the THALF or TNF interrupt.
3) Read THIR to obtain TFULL status.
4) Repeat Step 3.
5) Wait for interrupt, skip to Step 3.
6) Disable THALF or TNF interrupt and enable TMEND interrupt.
7) Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register.
a) If REMPTY = 0, then record OBYTE, CBYTE, and POK bits and then read the FIFO
b) If REMPTY = 1, then skip to Step 6
a) If TFULL = 0, then write a byte into the FIFO and skip to next step (special case occurs
b) If TFULL = 1, then skip to Step 5
a1) If CBYTE = 0 then skip to Step 5
a2) If CBYTE = 1 then skip to Step 7
when the last byte is to be written, in this case set TEOM = 1 before writing the byte and
then skip to Step 6)
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