DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 64

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address = 22 to 25 Hex)
Note: If CCR3.6 = 1, then a zero in the TCBRs implies that signaling data is to be sourced from TSER
(or TSIG if CCR3.2 = 1) and a one implies that signaling data for that channel is to be sourced from the
Transmit Signaling (TS) registers. See definition below.
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1
*CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm
bits.
17.
Each framer in the DS21Q44 contains dual two-frame (512 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the E1 data stream to 1.544Mbps (or a multiple of 1.544Mbps), which is the T1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock, which can be 1.544MHz or
2.048MHz. The backplane clock can burst at rates up to 8.192MHz. Both elastic stores contain full
controlled slip capability, which is necessary for this second purpose. Both elastic stores within a framer
are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to
them. The transmit side elastic store can be enabled whether the receive elastic store is enabled or
disabled and vice versa. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz
backplane without regard to the backplane rate the other elastic store is interfacing.
Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset (CCR6.0
and CCR6.1) function forces the elastic stores to a depth of one frame unconditionally. Data is lost during
the reset. The second method, the Elastic Store Align (CCR5.5 and CCR5.6) forces the elastic store depth
to a minimum depth of half a frame only if the current pointer separation is already less then half a frame.
If a realignment occurs data is lost. In both mechanisms, independent resets are provided for both the
receive and transmit elastic stores.
(MSB)
(MSB)
CH16
CH24
CH32
CH20
CH24
CH28
CH32
CH8
SYMBOL
CH1–32
ELASTIC STORES OPERATION
CH15
CH23
CH31
CH12
CH16
CH7
CH4
CH8
TCBR1.0–4.7
POSITION
CH14
CH22
CH30
CH19
CH23
CH27
CH31
CH6
CH21
CH15
CH13
CH29
CH11
CH5
CH3
CH7
Transmit Channel Blocking Control Bits
0 = force the TCHBLK pin to remain low during this channel
time
1 = force the TCHBLK pin high during this channel time
CH12
CH20
CH28
CH18
CH22
CH26
CH30
CH4
64 of 117
NAME AND DESCRIPTION
CH11
CH19
CH27
CH10
CH14
CH3
CH6
CH2
CH17*
CH10
CH18
CH26
CH21
CH25
CH29
CH2
(LSB)
(LSB)
CH17
CH25
CH1*
CH13
CH1
CH9
CH5
CH9
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)