DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 60

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1
CH20
CH24
CH28
CH32
*CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm
bits.
The user can also take advantage of this functionality to intermix signaling data from the TSIG pin and
from the internal Transmit Signaling Registers (TS1 to TS16). As an example, assume that the user
wishes to source all the signaling data except for voice channels 5 and 10 from the TSIG pin. In this
application, the following bits and registers would be programmed as follows:
15.
Each framer in the DS21Q44 can replace data on a channel–by–channel basis in both the transmit and
receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section
15.1. The receive direction is from the E1 line to the backplane and is covered in Section 15.2.
15.1. Transmit Side Code Generation
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 15.1.1 was a
feature contained in the original DS21Q43 while the second method which is covered in Section 15.1.2 is
a new feature of the DS21Q44.
15.1.1.
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8–bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel
in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle
Code contained in the Transmit Idle Definition Register (TIDR).
(MSB)
TCBFS = 1 (CCR3.6)
THSE = 1 (CCR3.2)
CONTROL BITS
T16S = 1(TCR1.5)
PER-CHANNEL CODE GENERATION AND LOOPBACK
CH4
CH8
CH12
CH16
Simple Idle Code Insertion and Per-Channel Loopback
CH19
CH23
CH27
CH31
TS1 = 0Bh (MF alignment word, remote alarm etc.)
TCBR1 = 03h (source timeslot 16, frame 1 data)
TCBR2 = 01h (source voice Channel 5 signaling data from TS6)
TCBR3 = 04h (source voice Channel 10 signaling data from TS11)
TCBR4 = 00h
CH3
CH7
CH11
CH15
CH18
CH22
CH26
CH30
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REGISTER VALUES
CH2
CH6
CH10
CH14
CH17*
CH21
CH25
CH29
(LSB)
CH1*
CH5
CH9
CH13
TCBR1(22)
TCBR2(23)
TCBR3(24)
TCBR4(25)