CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 11

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

Bit 1: BUSACTIVITY
If this interrupt is enabled, and the SX2 detects either an absence or resumption of activity on the USB bus, the SX2 asserts the
INT# pin and sets bit 1 in the Interrupt Status Byte. This usually indicates that the USB host is either suspending or resuming or
that a self-powered device has been plugged in or unplugged. If the SX2 is bus-powered, the external master must put the SX2
into a low-power mode after detecting a USB suspend condition to be USB-compliant.
Bit 0: READY
If this interrupt is enabled, bit 0 in the Interrupt Status Byte is set when the SX2 has powered up and performed a self-test. The
external master should always wait for this interrupt before trying to read or write to the SX2, unless an external EEPROM with
a valid descriptor is present. If an external EEPROM with a valid descriptor is present, the ENUMOK interrupt will occur instead
of the READY interrupt after power up. A READY interrupt will also occur if the SX2 is awakened from a low-power mode via the
WAKEUP pin. This READY interrupt indicates that the SX2 is ready for commands or data.
3.5
3.5.1
An input pin (RESET#) resets the chip. The internal PLL stabilizes approximately 7.6 ms after V
an external RC network (R = 100 K Ohms, C = 0.1 uf) is used to provide the RESET# signal.
3.5.2
When the SX2 detects a USB Reset condition on the USB bus, SX2 handles it like any other enumeration sequence. This means
that SX2 will enumerate again and assert the ENUMOK interrupt to let the external master know that it has enumerated. The
external master will then be responsible for configuring the SX2 for the application. The external master should also check whether
SX2 enumerated at High or Full speed in order to adjust the EPxPKTLENH/L register values accordingly. The last initialization
task is for the external master to flush all of the SX2 FIFOs.
3.5.3
The SX2 exits its low-power state when one of the following events occur:
3.6
3.6.1
3.6.2
Document #: 38-08013 Rev. *B
• USB bus signals a resume. The SX2 will assert a BUSACTIVITY interrupt.
• The external master asserts the WAKEUP pin. The SX2 will assert a READY interrupt.
• Control endpoint: 64 Bytes: 1 × 64 bytes (Endpoint 0).
• FIFO Endpoints: 4096 Bytes: 8 × 512 bytes (Endpoint 2, 4, 6, 8).
• EP0–Bidirectional Endpoint 0, 64-byte buffer.
• EP2, 4, 6, 8–Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and EP6 can be either double-, triple-, or quad-
buffered. EP4 and EP8 can only be double-buffered. For high-speed endpoint configuration options, see Figure 3-1.
Resets and Wakeup
Reset
USB Reset
Wakeup
Endpoint RAM
Size
Organization
CC
has reached 3.3V. Typically,
CY7C68001
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