CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 29

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

7.12
MICROFRAME contains a count 0–7 that indicates which of the 125 microsecond microframes last occurred.
This register is active only when SX2 is operating in high-speed mode (480 Mbits/sec).
7.13
During the USB enumeration process, the host sends a device a unique 7-bit address that the SX2 copies into this register. There
is normally no reason for the external master to know its USB device address because the SX2 automatically responds only to
its assigned address.
Bit 7: HSGRANT, Set to 1 if the SX2 enumerated at high speed. Set to 0 if the SX2 enumerated at full speed.
Bit[6..0]: Address set by the host.
7.14
This register is used to enable/disable the various interrupt sources, and by default all interrupts are enabled.
7.14.1
Setting this bit to a 1 enables an interrupt when a set-up packet is received from the USB host.
7.14.2
Setting this bit to a 1 enables an interrupt when the Endpoint 0 buffer becomes available.
7.14.3
Setting this bit to a 1 enables an interrupt when an OUT endpoint FIFO’s state transitions from empty to not-empty.
7.14.4
Setting this bit to a 1 enables an interrupt when SX2 enumeration is complete.
7.14.5
Setting this bit to a 1 enables an interrupt when the SX2 detects an absence or presence of bus activity.
7.14.6
Setting this bit to a 1 enables an interrupt when the SX2 has powered on and performed an internal self-test.
Document #: 38-08013 Rev. *B
MICROFRAME
Bit #
Bit Name
Read/Write
Reset
FNADDR
Bit #
Bit Name
Read/Write
Reset
ITENABLE
Bit #
Bit Name
Read/Write
Reset
MICROFRAME Registers 0x2C
FNADDR Register 0x2D
INTENABLE Register 0x2E
SETUP Bit 7
EP0BUF Bit 6
FLAGS Bit 5
ENUMOK Bit 2
BUSACTIVITY Bit 1
READY Bit 0
HSGRANT
SETUP
R/W
R
X
R
X
7
0
7
7
1
EP0BUF
R/W
FA6
R
R
6
0
X
6
X
6
1
FLAGS
R/W
FA5
R
R
5
0
X
5
X
5
1
ENUMOK
R/W
FA4
R
X
R
X
4
0
4
4
1
R/W
FA3
R
X
R
X
3
0
3
3
1
1
MF2
R/W
FA2
R
R
2
X
2
X
2
1
1
BUSACTIVITY
MF1
R/W
FA1
R
X
R
X
1
1
1
1
CY7C68001
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READY
MF0
R/W
FA0
R
R
X
0
x
0
0
1
0x2C
0x2D
0x2E