CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 12

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

3.6.3
Endpoint 0 is the same for every configuration as it serves as the CONTROL endpoint. For Endpoints 2, 4, 6, and 8, refer to
Figure 3-1. Endpoints 2, 4, 6, and 8 may be configured by choosing either:
Some example endpoint configurations are as follows.
3.6.4
At power-on-reset, the endpoint memories are configured as follows:
3.7
The SX2 presents two interfaces to the external master.
3.7.1
The SX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories and are
controlled by FIFO control signals (IFCLK, CS#, SLRD, SLWR, SLOE, PKTEND, and FIFOADR[2:0]).
The SX2 command interface is used to set up the SX2, read status, load descriptors, and access Endpoint 0. The command
interface has its own READY signal for gating writes, and an INT# signal to indicate that the SX2 has data to be read, or that an
interrupt event has occurred. The command interface uses the same control signals (IFCLK, CS#, SLRD, SLWR, SLOE, and
FIFOADR[2:0]) as the FIFO interface, except for PKTEND.
Document #: 38-08013 Rev. *B
1. A FIFO interface through which EP2, 4, 6, and 8 data flows.
2. A command interface, which is used to set up the SX2, read status, load descriptors, and access Endpoint 0.
• One configuration from Group A and one from Group B
• One configuration from Group C.
• EP2: 1024 bytes double-buffered, EP6: 512 bytes quad-buffered.
• EP2: 512 bytes double-buffered, EP4: 512 bytes double-buffered, EP6: 512 bytes double-buffered, EP8: 512 bytes double
• EP2: 1024 bytes quad-buffered.
• EP2: Bulk OUT, 512 bytes/packet, 2x buffered.
• EP4: Bulk OUT, 512 bytes/packet, 2x buffered.
• EP6: Bulk IN, 512 bytes/packet, 2x buffered.
• EP8: Bulk IN, 512 bytes/packet, 2x buffered.
buffered.
E P 0 IN & O U T
Endpoint Configurations (High-speed Mode)
Default Endpoint Memory Configuration
External Interface
Architecture
E P 2
E P 4
E P 6
E P 8
G r o u p A
G r o u p B
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
6 4
E P 2
E P 6
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
6 4
Figure 3-1. Endpoint Configuration
E P 2
E P 6
1 0 2 4
1 0 2 4
1 0 2 4
1 0 2 4
6 4
E P 2
E P 6
E P 8
G ro u p C
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
5 1 2
6 4
E P 2
E P 8
1 0 2 4
1 0 2 4
1 0 2 4
5 1 2
5 1 2
6 4
E P 2
CY7C68001
1 0 2 4
1 0 2 4
1 0 2 4
1 0 2 4
6 4
Page 12 of 50