CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 42

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

For a burst write the SLWR is left asserted during the entire duration of writing all the required bytes. In this burst write mode once
the SLWR is asserted the data on the FIFO data bus is written to the FIFO on every rising edge of the IFLCLK. The FIFO pointer
is also updated on each rising edge of the IFCLK. In the above diagram once the four bytes are written to the FIFO, the SLWR
is de-asserted. The short 4-byte packet can be committed to the host using the PKTEND pin.
There is no specific timing requirement that needs to be met for asserting PKTEND pin with regards to asserting SLWR signal.
The PKTEND pin can be asserted anytime. In the scenario above the number of packets committed include the byte written last
to the FIFO on the same rising edge of the IFCLK as the PKTEND is asserted. The FIFOADDR lines should be held constant
during the PKTEND pin assertion.
11.6.3
The above sequence and timing diagram shows the timing relation between various signals while performing a read from the
FIFO in asynchronous mode. The diagram shows a single read followed by a burst read.
Document #: 38-08013 Rev. *B
FLAGS
FIFOADR
FIFO POINTER
• Asserting the SLWR causes the data on the data bus to be written to the FIFO and the FIFO pointer incremented. The flag is
• At t = 0 the FIFO address is set.
• SLOE is asserted. This causes the data lines to be in a driven state. The data output is the previous data, whatever was output
• The SLRD and SLCS is asserted at the same time. The SLRD must meet the minimum active pulse of t
• The data that is output on asserting the SLRD is the actual data from the FIFO. This data is output after a propagation delay
SLRD/
SLCS
SLCS
DATA
FIFO DATA BUS Not Driven
SLOE
asserted state when SLWR is also asserted. The internal logic ANDs these two signals to determine a valid condition. Hence
these signals can also be tied together.
also updated after t
last time around.
de-active pulse width of t
internal logic basically ANDs these two signal to determine a valid condition. Hence these signals can be tied together.
of t
When the SLRD is asserted, in order to have the data output on the FIFO data bus, the SLOE MUST be in an asserted state
also. The SLRD and SLOE can also be tied together.
XFD
Sequence Diagram of a Single and Burst Asynchronous Read
from the activating edge of the SLRD. So in the above diagram data N is the actual first byte data read from the FIFO.
t=0
N
Driven
Data (X)
Figure 11-18. Slave FIFO Asynchronous Read Sequence and Timing Diagram
t
SFA
t
XFLG
OEon
Figure 11-19. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLOE
t
RDpwl
from the rising edge of the clock.
RDpwh
Driven: X
t
XFD
N
N
t
RDpwh
. If SLCS is used then, SLCS must be in an asserted state when SLRD is also asserted. The
t
FAH
SLRD
t
t
OEoff
XFLG
N
N
SLRD
N+1
N
SLOE
t
t
SFA
OEon
N
Not Driven
N+1
t
RDpwl
t
XFD
SLOE
t
N+1
RDpwh
N+1
N
SLRD
t
RDpwl
t
XFD
N+1
N+1
SLRD
t
N+2
RDpwh
N+2
N+1
SLRD
t
RDpwl
t
XFD
N+3
N+2
N+2
t
t
RDpwh
FAH
SLRD
t
OEoff
t
XFLG
N+3
N+2
RDpwl
CY7C68001
SLOE
and minimum
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Not Driven
N+3