CY7C68001-56LTXC Cypress Semiconductor Corp, CY7C68001-56LTXC Datasheet - Page 21

• Manufacturer Part Number: CY7C68001-56LTXC
• Description: IC USB EZ-USB SX2 HS 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USBr

Specifications of CY7C68001-56LTXC

• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2932

7.0
Table 7-1. SX2 Register Summary
*Please note that the SX2 was not designed to support dynamic modification of these endpoint configuration registers. If your
applications need the ability to change endpoint configurations after the device has already enumerate with a specific configu-
ration, please expect some delay in being able to access the FIFOs after changing the configuration. For example, after writing
to EP2PKTLENL, you must wait for at least 35 us measured from the time the READY signal is asserted before writing to the
FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic
change of endpoint configuration registers.
Document #: 38-08013 Rev. *B
Hex Size Name
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
2A
2B
2C
2D
2E
30
31
32
33
500 DESC
8/1 SETUP
64 EP0BUF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
General Configuration
IFCONFIG
FLAGSAB
FLAGSCD
POLAR
REVID
*Endpoint Configuration
EP2CFG
EP4CFG
EP6CFG
EP8CFG
EP2PKTLENH Endpoint 2 Packet Length H
EP2PKTLENL
EP4PKTLENH Endpoint 4 Packet Length H
EP4PKTLENL
EP6PKTLENH Endpoint 6 Packet Length H
EP6PKTLENL
EP8PKTLENH Endpoint 8 Packet Length H
EP8PKTLENL
EP2PFH
EP2PFL
EP4PFH
EP4PFL
EP6PFH
EP6PFL
EP8PFH
EP8PFL
EP2ISOINPKTS EP2 (if ISO) IN Packets per frame (1-3)
EP4ISOINPKTS EP4 (if ISO) IN Packets per frame (1-3)
EP6ISOINPKTS EP6 (if ISO) IN Packets per frame (1-3)
EP8ISOINPKTS EP8 (if ISO) IN Packets per frame (1-3)
FLAGS
EP24FLAGS
EP68FLAGS
INPKTEND/FLUSH
INPK-
TEND/FLUSH
USB Configuration
USBFRAMEH
USBFRAMEL
MICROFRAME Microframe count, 0-7
FNADDR
Interrupts
INTENABLE
Descriptor
Endpoint 0
EP0BC
Register Summary
Description
Interface Configuration
FIFO FLAGA and FLAGB Assign-
ments
FIFO FLAGC and FLAGD Assign-
ments
FIFO polarities
Chip Revision
Endpoint 2 Configuration
Endpoint 4 Configuration
Endpoint 6 Configuration
Endpoint 8 Configuration
Endpoint 2 Packet Length L (IN only)
Endpoint 4 Packet Length L (IN only)
Endpoint 6 Packet Length L (IN only)
Endpoint 8 Packet Length L (IN only)
EP2 Programmable Flag H
EP2 Programmable Flag L
EP4 Programmable Flag H
EP4 Programmable Flag L
EP6 Programmable Flag H
EP6 Programmable Flag L
EP8 Programmable Flag H
EP8 Programmable Flag L
Endpoints 2,4 FIFO Flags
Endpoints 6,8 FIFO Flags
Force Packet End / Flush FIFOs
USB Frame count H
USB Frame count L
USB Function address
Interrupt Enable
Descriptor RAM
Endpoint 0 Buffer
Endpoint 0 Set-up Data / Stall
Endpoint 0 Byte Count
IFCLKSRC 3048MHZ
HSGRANT
FLAGB3
FLAGD3
WUPOL
SETUP
INFM1
INFM1
INFM1
INFM1
DECIS
DECIS
DECIS
DECIS
VALID
VALID
FIFO8
VALID
VALID
Major
PFC7
PFC7
PFC7
PFC7
FC7
PL7
PL7
PL7
PL7
D7
d7
d7
d7
d7
0
0
0
0
0
0
0
0
PKTSTAT
PKTSTAT
PKTSTAT IN:PKTS[2]
PKTSTAT IN:PKTS[2]
FLAGB2
FLAGD2
EP0BUF
EP4PF
EP8PF
FIFO6
OEP1
OEP1
OEP1
OEP1
Major
PFC6
PFC6
PFC6
PFC6
FC6
PL6
PL6
PL6
PL6
FA6
D6
dir
dir
dir
dir
d6
d6
d6
d6
0
0
0
0
0
0
0
OUT:PFC12
OUT:PFC12
ZEROLEN
ZEROLEN
ZEROLEN
ZEROLEN
IFCLKOE
PKTEND
FLAGB1
FLAGD1
FLAGS
TYPE1
TYPE1
TYPE1
TYPE1
EP4EF
EP8EF
FIFO4
Major
PFC5
PFC5
PFC5
PFC5
FC5
PL5
PL5
PL5
PL5
FA5
D5
d5
d5
d5
d5
0
0
0
0
0
0
0
0
OUT:PFC11
IN: PKTS[1]
OUT:PFC10
OUT:PFC11
IN: PKTS[1]
OUT:PFC10
IN:PKTS[1]
IN:PKTS[1]
IFCLKPOL
FLAGB0
FLAGD0
WORD-
WORD-
WORD-
WORD-
TYPE0
TYPE0
TYPE0
TYPE0
EP4FF
EP8FF
FIFO2
SLOE
WIDE
WIDE
WIDE
WIDE
Major
PFC4
PFC4
PFC4
PFC4
FC4
PL4
PL4
PL4
PL4
FA4
D4
d4
d4
d4
d4
0
0
0
0
0
0
1
OUT:PFC10
IN: PKTS[0]
OUT:PFC10
IN: PKTS[0]
IN:PKTS[0]
IN:PKTS[0]
OUT:PFC9
OUT:PFC9
FLAGC3
FLAGA3
ASYNC
SLRD
minor
PFC3
PFC3
PFC3
PFC3
SIZE
SIZE
EP3
FC3
FA3
PL3
PL3
PL3
PL3
D3
d3
d3
d3
d3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
STANDBY FLAGD/CS#
ENUMOK BUSACTIVI-
FLAGC2
FLAGA2
EP2PF
EP6PF
STALL
STALL
STALL
STALL
SLWR
PFC2
PFC2
PFC2
PFC2
minor
FC10
PL10
PL10
MF2
PL2
PL2
PL2
EP2
FC2
FA2
PL2
D2
d2
d2
d2
d2
0
0
0
0
0
0
0
0
0
0
FLAGA1
FLAGC1
INPPF1
INPPF1
INPPF1
INPPF1
EP2EF
EP6EF
minor
BUF1
BUF1
PFC9
PFC1
PFC1
PFC9
PFC1
PFC1
MF1
EP1
FC9
FC1
FA1
PL9
PL1
PL9
PL1
PL9
PL1
PL9
PL1
D1
EF
TY
d1
d1
d1
d1
0
0
0
0
DISCON
FLAGC0
FLAGA0
INPPF0
INPPF0
INPPF0
INPPF0
READY
EP2FF
EP6FF
PFC8
PFC0
PFC0
PFC8
PFC0
PFC0
minor
BUF0
BUF0
PFC8
PFC8
MF0
PL8
PL0
PL8
PL0
PL8
PL0
PL8
PL0
EP0
FC8
FC0
FA0
D0
FF
d0
d0
d0
d0
CY7C68001
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0
Page 21 of 50
00000000
00000000
00000000
10100010
10100000
00000000
00000000
00000000
00000000
10001000
00000000
10001000
00000000
00001000
00000000
00001000
00000000
00000001
00000001
00000001
00000001
00100010
00000000
11001001
11100010
11100000
00110010
00110010
00110010
00110010
01100110
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
11111111
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
Default
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
R
R
R
R
R