PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 23

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.3
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The program counter
is 13 bits wide. The low byte is called the PCL register.
The PCL register is readable and writable. The high
byte of the PC (PC<12:8>) is called the PCH register.
This register contains PC<12:8> bits which are not
directly readable or writable. All updates to the PCH
register goes through the PCLATH register.
On any Reset, the PC is cleared. Figure 2-3 shows the
two situations for loading the PC. The upper example
of Figure 2-3 shows how the PC is loaded on a write to
PCL (PCLATH<4:0>
Figure 2-3 shows how the PC is loaded during a CALL
or GOTO instruction (PCLATH<4:3>
2.3.1
Executing any instruction with the PCL register as the
destination
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register, all
13 bits of the program counter will change to the values
contained in the PCLATH register and those being
written to the PCL register.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
2.3.2
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When using a CALL or GOTO instruction,
the Most Significant bits of the address are provided by
PCLATH<4:3> (page select bits). When using a CALL
or GOTO instruction, the user must ensure that the page
select bits are programmed so that the desired destina-
tion program memory page is addressed. When the
CALL instruction (or interrupt) is executed, the entire
13-bit PC return address is PUSHed onto the stack.
Therefore, manipulation of the PCLATH<3> bit is not
required for the RETURN or RETFIE instructions (which
POPs the address from the stack).
© 2006 Microchip Technology Inc.
PCL and PCLATH
MODIFYING PCL
PROGRAM MEMORY PAGING
simultaneously causes the
PCH). The lower example of
PCH).
Program
Preliminary
FIGURE 2-3:
2.3.3
The PIC16F785/HV785 family has an 8-level deep x
13-bit wide hardware stack (see Figure 2-1). The stack
space is not part of either program or data space and
the Stack Pointer is not readable or writable. The PC is
PUSHed onto the stack when a CALL instruction is
executed or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLW or RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
PC
PC
Note 1: There are no Status bits to indicate stack
12
12 11 10
2
PIC16F785/HV785
2: There are no instructions/mnemonics
5
PCH
PCLATH<4:3>
PCH
STACK
overflow or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
PCLATH
PCLATH<4:0>
8
PCLATH
8
7
7
LOADING OF PC IN
DIFFERENT SITUATIONS
PCL
PCL
11
8
DS41249D-page 21
0
0
Opcode <10:0>
ALU result
GOTO, CALL
Instruction with
Destination
PCL as