PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 64

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F785/HV785
8.3.3
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the RC5/CCP1 pin is driving a value, it will
continue to drive that value. When the device wakes
up, it will continue from this state.
8.3.3.1
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the CCP to be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See Section 3.0 “Clock Sources” for additional
details.
8.3.4
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 8-4:
DS41249D-page 62
0Bh,
8Bh
0Ch
11h
12h
13h
14h
15h
87h
8Ch
92h
Legend:
Addr
INTCON
PIR1
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
TRISC
PIE1
PR2
Name
OPERATION IN SLEEP MODE
EFFECTS OF RESET
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the CCP or Timer2 modules.
OPERATION WITH FAIL-SAFE
CLOCK MONITOR
Timer2 Module Register
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
Timer2 Module Period Register
TRISC7
REGISTERS ASSOCIATED WITH CCP AND TIMER2
EEIE
Bit 7
EEIF
GIE
—
—
TOUTPS3 TOUTPS2
TRISC6
ADIE
Bit 6
PEIE
ADIF
—
CCP1IE
CCP1IF
TRISC5
DC1B1
Bit 5
T0IE
TOUTPS1
TRISC4
DC1B0
INTE
Bit 4
C2IF
C2IE
Preliminary
TOUTPS0
CCP1M3
TRISC3
RAIE
C1IE
Bit 3
C1IF
8.3.5
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
6.
TMR2ON T2CKPS1 T2CKPS0
CCP1M2
TRISC2
OSFIE
OSFIF
Configure the PWM pin (RC5/CCP1) as an input
by setting the TRISC<5> bit.
Set the PWM period by loading the PR2 register.
Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
• Set the TMR2 prescale value by loading the
• Enable Timer2 by setting the TMR2ON bit
Enable PWM output after a new PWM cycle has
started:
• Wait until TMR2 overflows (TMR2IF bit is
• Enable the RC5/CCP1 pin output by clearing
Bit 2
T0IF
set).
the TRISC<5> bit.
the TMR2IF bit (PIR1<1>).
T2CKPS bits (T2CON<1:0>).
(T2CON<2>).
SETUP FOR PWM OPERATION
CCP1M1
TMR2IE
TMR2IF
TRISC1
Bit 1
INTF
CCP1M0
TMR1IF
TMR1IE
TRISC0
RAIF
Bit 0
© 2006 Microchip Technology Inc.
0000 0000
0000 0000
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
0000 0000
--11 1111
0000 0000
1111 1111
POR, BOR
Value on:
0000 0000
0000 0000
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
0000 0000
--11 1111
0000 0000
1111 1111
Value on
all other
Resets