PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 70

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PIC16F785-I/P

Manufacturer Part Number
PIC16F785-I/P
Description
MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F785-I/P

A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
17
Memory Type
Flash
Number Of Bits
8
Package Type
20-pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
PIC16F785/HV785
9.1.2.2
Comparator C2 has one additional feature: its output
can be synchronized to the Timer1 clock input. Setting
C2SYNC (CM2CON1<0>) synchronizes the output of
Comparator 2 to the falling edge of the Timer1 clock
input (see Figure 9-2 and Register 9-3).
The CM2CON1 register also contains mirror copies of
both comparator outputs, MC1OUT and MC2OUT
(CM2CON1<7:6>). The ability to read both outputs
simultaneously from a single register eliminates the
timing skew of reading separate registers.
REGISTER 9-3:
DS41249D-page 68
Note:
bit 7
bit 6
bit 5-2
bit 1
bit 0
Obtaining the status of C1OUT or C2OUT
by reading CM2CON1 does not affect the
comparator interrupt mismatch registers.
Control Register CM2CON1
CM2CON1: COMPARATOR C2 CONTROL REGISTER 1 (ADDRESS: 11Bh)
bit 7
MC1OUT: Mirror Copy of C1OUT bit (CM1CON0<6>)
MC2OUT: Mirror Copy of C2OUT bit (CM2CON0<6>)
Unimplemented: Read as ‘0’
T1GSS: Timer1 Gate Source Select bit
1 = Timer1 gate source is RA4/AN3/T1G/OSC2/CLKOUT
0 = Timer1 gate source is SYNCC2OUT.
C2SYNC: C2 Output Synchronous Mode bit
1 = C2 output is synchronous to falling edge of TMR1 clock
0 = C2 output is asynchronous
MC1OUT MC2OUT
Legend:
R = Readable bit
-n = Value at POR
R-0
R-0
U-0
Preliminary
W = Writable bit
‘1’ = Bit is set
U-0
U-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
T1GSS
R/W-1
C2SYNC
R/W-0
bit 0

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