PIC16F785-I/P Microchip Technology Inc., PIC16F785-I/P Datasheet - Page 39

• Manufacturer Part Number: PIC16F785-I/P
• Description: MCU, 8-Bit, 2KW Flash, 128 RAM, 18 I/O, DIP-20
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F785-I/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 17
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.2.2
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 4-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set, the PORTA Change Interrupt flag
bit (RAIF) in the INTCON register (Register 2-3).
REGISTER 4-4:
© 2006 Microchip Technology Inc.
bit 7-6
bit 5-0
INTERRUPT-ON-CHANGE
IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER (ADDRESS: 96h)
bit 7
Unimplemented: Read as ‘0’
IOCA<5:0>: Interrupt-on-change PORTA Control bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Legend:
R = Readable bit
-n = Value at POR
Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be
U-0
—
2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
recognized.
U-0
—
IOCA5
R/W-0
Preliminary
W = Writable bit
‘1’ = Bit is set
(2)
IOCA4
R/W-0
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the inter-
rupt by:
a)
b)
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared. The latch holding the
last read value is neither affected by an MCLR nor BOR
Reset. After these resets, the RAIF flag will continue to
be set if a mismatch is present.
Note:
(2)
Any read or write of PORTA. This will end the
mismatch condition, then,
Clear the flag bit RAIF.
PIC16F785/HV785
IOCA3
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
(2)
IOCA2
R/W-0
x = Bit is unknown
IOCA1
R/W-0
DS41249D-page 37
(1)
IOCA0
R/W-0
bit 0